Table of Contents
Advertisement
HP 27130B
Table 3-9. Interrupt Vector Bits
VECTOR BIT5
LMAA
I11AB
II NT
2
1
0
1
X
X
0
0
0
0
1
X
0
1
0
0
0
1
1
0
0
X
=
Don't care
Priority Interrupt Structure
All I/O devices connected to the MUX card can cause interrupts. These interrupts are prioritized
according to the standard Z-80 priority chain. There is no non-maskable interrupt used on the
MUX card. Interrupts from the host computer (via the BIC) to the MUX are prioritized within the
MIC circuit. The MUX card interrupt priority structure is as follows:
Highest Priority
510/2 Number 0, Channel A
510/2 Number 0, Channel B
510/2 Number
1 ,
Channel A
510/2 Number
1 ,
Channel
B
510/2 Number 2, Channel A
510/2 Number 2, Channel B
510/2 Number
3,
Channel A
510/2 Number
3,
Channel B
BIC
CTC Number 0, Channel 0
MIC IJ1A Channel A
Lowest Priority
MIC IJ1A Channel B
Wait State Circuits for Interrupt Acknowledge
On the MUX card, six devices (SIO 0, SIO 1, SIO 2, SIO 3, CTC 0, and MIC) are connected in a daisy
chain interrupt structure. Due to the delay of the long daisy chain, a wait state must be added
during an interrupt acknowledge cycle in order to conform to the timing requirements of the Z-80B
CPU.
3-28
Advertisement
Table of Contents
