Table of Contents
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CONTENTS
- - - - - - -
Section I
GENERAL INFORMATION
I nt roduct ion .............................................................. 1 -1
Physical Description
1-1
Functional Description .................................................... 1-1
Eguipment Supplied
1-3
Options Available .......................... ' ............................... 1-3
Product and Part Identification
1-3
The Product ............................................................. 1 -3
Printed Circuit Card
1-3
r1anuals ................................................................. 1-4
Specifications
1-4
SectionII
INSTALLATION
Determining Current Requirements .......................................... 2-1
Firmware (EPROM) Installation
2-1
Jumpers ................................................................... 2-3
Memory Configuration Jumper
2-3
Signature Analysis Jumper ............................................... 2-5
lID
Channel Interface
2-5
Per ipheral Device Interface ................. 0 . 0 .. 0 0 .. 0 ... 0 0 ............... 2-5
Extension Cable Fabr icat ion ........... 0 .0 .0 ..
o • •
00' ...
o • • • •
0 ... 0 .. 00 .... 02-11
Installing the MUX
2-11
Opt ional Brackets 0 ......
o .
0 ... 00 ..... 00 ................ 0 0 .. 0
o • • • • • • • •
o • • •
2-12
Start-up
2-16
Reshipment .............................
o.
0 ............... ' ................ 2-16
Section III
PRINCIPLES OF OPERATION
Funct ional descr ipt i on ........................................... 0 . 0 ...... 3-1
System Clocks
3-3
Memory Address Space ... 0 . '0' ....... 0 .......
o • • • • • • • • • • • • • • • • • • • • • • • • • • • •
3-3
I/O Address Space
3-6
Z-80B Microprocessor CPU
3-6
Z-80 SIO/2 (Serial
lID
Controller)
3-6
CTC (Counter Timer Circuit ........... 0 ........................... 0 ..... 3-19
Interfacing to the BIC
3-19
Memory Interface Circuit (MIC)
3-24
Regi ster .......... 0 ............................... 0 ... 0 ............... 0 ... 03-24
o -
MIC Configuration
3-24
1 - DMA B Upper Byte of Mem Addr
3-24
2 - DMA Lower Byte of Memory Address
3-24
3 - Dt1A B Conf igura t ion. 0 . 0 .... 0 ... 0 . 0 0 0 .... 0 .. 0 . 0 0 .................. 3-24
4 - Lower Byte of Trans Byt Cnt, Channel B
3-2
5 - DMA
B
I/O Port Address ........ 0 .... 0 ............................. 3-25
6 -
DMA A Upper Byte of Memory Address .......... 0 ..... 0 ........ 0 ..... 3-25
7 - DMA A Lower Byte of Mem Addr
3-25
8 - DMA A Configuration
3-26
9 - Lower Byte of Trans Byt Cnt, Channel A ... 0 ... 0 .............. 0 ..... 3-2
A -
DMA A I/O Port Address
3-26
B - Interrupt Vector ............. 0 ...................... 0 ............ 3-26
111
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Table of Contents
