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I²C-bus autosync deflection controller for PC monitors
Frequency-locked loop
The frequency-locked loop can lock the horizontal oscilla-
tor over a wide frequency range. This is achieved by a com-
bined search and PLL operation. The frequency range is
preset by two external resistors and the
recommended maximum ratio is
This can, for instance, be a range from 15.625 to 90kHz
with all tolerance included.
Without a horizontal sync signal the oscillator will be free-
running at f
. Any change of sync conditions is detected
min
by the internal coincidence detector. A deviation of more
than 4% between horizontal sync and oscillator frequency
switches the horizontal section into search mode. This
means that PLL1 control currents are switched off
immediately. The internal frequency detector then starts
tuning the oscillator. Very small DC currents at HPLL1 (pin
26) are used to perform this tuning with a well defined
change rate. When coincidence between horizontal sync
and oscillator frequency is detected, the search mode is
first replaced by a soft-lock mode which lasts for the first
part of the next vertical period.
The soft-lock mode is then replaced by a normal PLL
operation. This operation ensures smooth tuning and avoids
fast changes of horizontal frequency during catching.
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed inter-
nally to HBUF (pin 27) via a sample-and-hold and buffer
stange. The sample-and-hold stage removes all distur-
bances caused by horizontal sync or composite vertical sync
from the buffered voltage. An external resistor connected
between pins HBUF and HREF defines the frequency range.
Out-of-lock indication (pin HUNLOCK)
Pin HUNLOCK is floating during search mode, or if a pro-
tection condition is true. All this can be detected by the
microcontroller if a pull-up resistor is connected to its own
supply voltage.
For an additional fast vertical blanking at grid 1 of the pic-
ture tube a 1 V signal referenced to ground is available at
this output. The continuous protection blanking (see Sec-
tion "Video clamping/vertical blanking generator") is also
available at this pin. Horizontal unlock blanking can be
switched off, by control bit BLKDIS via the I²C-bus while
vertical blanking is maintained.
f
max
6.5
=
1
f
max
Horizontal oscillator
The horizontal oscillator is of the relaxation type and re-
quires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must not
be changed.
The minimum oscillator frequency is determined by a re-
sistor from HREF to ground. A resistor connected between
pins HREF and HBUF defines the frequency range.
The reference current at pin HREF also defines the inte-
gration time constant of the vertical sync integration.
Calculation of line frequency range
The oscillator frequencies fmin and fmax must first be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync fre-
quencies f
and f
sync(min)
currents in R
and R
HREF
The following example is a 31.45 to 90 kHz application:
Table 1 Calculation of total spread
spread of
IC
C
HCAP
R
, R
HREF
HBUF
Total
Thus the typical frequency range of the oscillator in this
example is:
=
×
f
f
1.07
max
sync(max)
f
sync(min)
=
=
f
28.4
min
1.09
The resistors R
and R
HREF
the following formulae:
78
=
R
HREF
+
f
0.0012
min
=
R
HBUFpar
+
f
max
The resistor R
HBUF
par
and R
in parallel.
HBUF
61
TDA4857
. The oscillator is driven by the
sync(max)
HBUF.
for f
max
±3%
±2%
±2%
±7%
=
96.3
kHz
kHz
can be calculated using
HBUF
par
×
×
kHz
kÙ
=
2.61 Ù
[ ]
2
×
f
kHz
min
×
×
78
kHz
kÙ
=
[ ]
2
×
0.0012
f
kHz
max
os calculated as the value to R
for f
min
±5%
±2%
±2%
±9%
726Ù
HREF
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