NEC MultiSync 75F-3 Service Manual page 63

I²C-bus autosync deflection controller for PC monitors
FUNCTIONAL DESCRIPTION
Horizontal sync separator and polarity correction
HSYNC (pin 15) is the input for horizontal synchronization
signals, which can be DC-coupled TTL signals (horizontal
or composite sync) and AC-coupled negative-going video
sync signal. Video syncs are clamped to 1.28V and sliced
at 1.4V. This results in a fixed absolute slicing level of 120
mV related to top sync.
For DC-coupled TTL signals the input clamping current is
limited. The slicing level for TTL signals is 1.4 V.
The separated sync signal (either video or TTL) is integrated
on an internal capacitor to detect and normalize the sync
polarity.
Normalized horizontal sync pulses are used as input sig-
nals for the vertical sync integrator, the PLL1 phase detec-
tor and the frequency-locked loop.
Vertical sync integrator
Normalized composite sync signals from HSYNC are inte-
grated on an internal capacitor in order to extract vertical
sync pulses. The integration time is dependent on the hori-
zontal oscillator reference current at HREF (pin 28). The
integrator output directly triggers the vertical oscillator.
Vertical sync slicer and polarity correction
Vertical sync signals (TTL) applied to VSYNC (pin 14) are
sliced at 1.4V. The output signal of the sync slicer is inte-
grated on an internal capacitor to detect and normalize the
sync polarity. The output signals of vertical sync integrator
and sync normalizer are disjuncted before they are fed to
the vertical oscillator.
Video clamping/vertical blanking generator
The video clamping/vertical blanking signal at CLBL (pin
16) is a two-level sandcastle pulse which is especially suit-
able for video ICs such as the TDA488x family, but also for
direct applications in video output stages.
The upper level is the video clamping pulse, which is trig-
gered by the horizontal sync pulse. Either the leading or
trailing edge can be selected by setting control bit CLAMP
via the I²C-bus. The width of the video clamping pulse is
determined by an internal single-shot multivibrator.
The lower level of the sandcastle pulse is the vertical blank-
ing pulse, which is derived directly from the internal oscilla-
tor waveform. It is started by the vertical sync and stopped
with the start of the vertical scan. This results in optimum
vertical blanking. Two different vertical blanking times are
accessible, by control bit VBLK, via the I²C-bus.
Blanking will be activated continuously if one of the follow-
ing conditions is true:
Soft start of horizontal and B+ drive [voltage at HPLL2
(pin 30) pulled down externally or by the I²C-bus]
PLL1 is unlocked while frequency-locked loop is in
search mode
No horizontal flyback pulses at HFLB (pin 1)
X-ray protection is activated
Supply voltage at Vcc (pin 10) is low
Horizontal unlock blanking can be switched off, by control
bit BLKDIS, via the I²C-bus while vertical blanking is
maintained.
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TDA4857