I-Sgpio1/2 Headers; Standby Power Header - Supermicro X10DRL-CT User Manual

X10DRL-CT/-iT/-C Motherboard User's Manual

I-SGPIO1/2 Headers

Two SGPIO (Serial Link General Pur-
pose Input/Output) headers are locat-
ed on the motherboard. I-SGPIO1/2
support onboard I-SATA0-5 connec-
tions. See the table on the right for
pin definitions.

Standby Power Header

The +5V Standby Power header is
located at JSTBY1 on the mother-
board. See the table on the right for
pin definitions. (You must also have a
card with a Standby Power connector
and a cable to use this feature.)
A. I-SGPIO1
B. I-SGPIO2
C. Standby PWR
LEDBMC
JL1
1
JPF1
JPF2
JPG1
JBR1
CMOS CLEAR
JS18
J25
A
I-SGPIO1
JPS7
JF1
L-SAS0-3
L-SAS4-7
B
LEDPWR
JUIDB1
FAN6
1
LAN3
LAN4
24
JL1
CHASSIS INTRUSION
JBR1
1-2:NORMAL
2-3:BIOS RECOVERY
JPTG1:10Gb LAN
1-2 ENABLE
2-3 DISABLE
JPME2
1-2:NORMAL
2-3:ME MANUFACTURING MODE
JI2C1/JI2C2
I2C BUS FOR PCI-E SLOT
1-2:ENABLE
2-3:DISABLE
JPB1:BMC
1-2 ENABLE
2-3 DISABLE
JPL1/ JPL2 LAN
1-2 ENABLE
2-3 DISABLE
JI2C2
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
REV:1.00
X10DRL-CT
DESIGNED IN USA
SAN MAC
SAS CODE
BT1
C
JTPM1
JD1:
JTPM1:TPM/PORT80
PWR LED-PIN 1-3
SPEAKER-PIN 4-7
JPS1:SAS
1-2 ENABLE FAN2
2-3 DISABLE
J5 J7
PWR RST X OH/ NIC NIC HDD PWR X NMI
1-2:RST
JWD1:WATCH DOG
ON FF 2 1 LED LED
2-3:NMI
2-30
I-SGPIO Headers
Pin Definitions
Pin# Definition
1 NC
3 Ground
5 Load
7 Clock
Note: NC= No Connection
I-SGPIO0/1 & S-SGPIO Support
I-SGPIO1 I-SATA Ports 0/1/2/3 Supported
I-SGPIO2 I-SATA Ports 4/5 Supported
Standby PWR
Pin Definitions
Pin#
1
2
3
JVGA
VGA
USB12/13(3.0)
JPL2
IPMI_LAN
LAN1
LAN2
JLAN1
CPU2
BIOS LICENSE
Pin Definition
2 NC
4 Data
6 Ground
8 NC
Definition
+5V Standby
Ground
No Connection
JPL1
J21
13
1
24 12
FAN1
JPWR1