Icom IC-91A Service Manual page 15

• B_BAND PLL CIRCUIT
The buffer amplified signals from the buffer amplifier (MAIN UNIT;
Q353) are applied to the PLL IC (MAIN UNIT; IC400, pin 8). The
applied signals are divided at the prescaler and OSC counter
according to the "PLLDATA" signal from the CPU (LOGIC UNIT;
IC1, pin 94). The divided signal is phasecompared with the
reference frequency at the phase detector.
The phase difference is output from pin 5 as a pulse type signal
after being passed through the charge pump. The output signal is
• B_BAND PLL AND VCO CIRCUITS
VBVCO
Q301,D300,D301
UBVCO
Q351,D350,D352
Loop filter
"BPS" signal to the CPU
(LOGIC UNIT; IC1, pin 93)
15.3 MHz "REF"
signal to the PLL IC
(RF UNIT; IC800, pin 6)
×3
45.9 MHz
D450
Q451
2nd LO signal
Q452
15.3/61.2 MHz
×4
2nd LO signal
5-4 DIGITAL CIRCUITS
5-4-1 LINER CODEC
(UT-121; CODEC UNIT for IC-91AD)
IC350 is a liner codec IC which converts transmitting AF signals
from the LOGIC unit into digital signals, and outputs them to the
audio codec IC (IC101) as 16-bit audio data.
IC350 also converts the 16-bit audio data from the audio codec IC
(IC101) into analog signals, and outputs them to the LOGIC unit as
the receiving AF signals.
5-4-2 AUDIO CODEC
(UT-121; CODEC UNIT for IC-91AD)
IC101 is an AMBE audio codec IC. While receiving, digital signals
from the LOGIC unit are expansion decoded in IC101, and output
to the liner codec IC (IC350).
While transmitting, 16-bit audio data from the liner codec IC (IC350)
are compression coded in IC101, and output to the LOGIC unit.
5-4-3 MODEM (UT-121; CODEC UNIT for IC-91AD)
IC202 is a GMSK modem IC. While receiving, demodulated AF
signals from the MAIN unit are output to the LOGIC unit as digital
signals synchronized with clock signal.
While transmitting, digital signals from the LOGIC unit are converted
into GMSK base-band signal, and output to the LOGIC unit.
applied to the B_BAND VBVCO/UBVCO (MAIN UNIT) after being
converted into the DC voltage (lock voltage) at the loop filter (MAIN
UNIT; R404–R406, C410–C412, C414). The lock voltage from the
loop filter is applied to each VCO.
If the oscillated signal drifts, its phase changes from that of the
reference frequency, causing a lock voltage change to compensate
for the drift in the oscillated frequency.
PLL IC (IC400)
Phase
5 Charge
Pump Detector
12
Reference
Counter
1
Buffer
amp.
Q450
5 - 8
Buffer
amp.
Q353
OSC 5
Pre-
Counter
scaler
9
10
Input Register
11
TCXO
X450
15.3 MHz
1st LO signals to the
1st mixer (IC50, pin 3)
"CK"
PLL IC control signals
from the CPU
"PLLDATA"
(LOGIC UNIT; IC1)
"BPLSTB"
MAIN UNIT