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• Methods of Interpreting Whether Normal or Abnormal
Each terminal is normal if it is in the following status in the "READY" condition after run by BASIC.
Pin No. of IC
Normal condition
ICl
®
Negative pulse
Same as MI (CPU bus)
ICl
CID
Positive pulse
Reversed MI (CPU bus)
ICl
@
Constant L level
IC2
(j))
Positive pulse
Reversed
MT
(CPU bus)
IC2
®
Reversed buscJI
IC3
@
Constant H level
IC5
CD
Positive pulse
(Turns H level when XXCOH to XXC7H are transmitted
address bus.)
IC5
<V
Positive pulse
Reversed RD (CPU bus)
IC5
@
Positive pulse
Reversed 10RQ (CPU bus)
IC5
@
Positive pulse
Reversed MI. (CPU bus)
IC5
@
Constant L level
IC6
CD
Constant H level
IC7
@
Constant H level
IC7
@
Constant H level
.
IC7
@
Constant H level
IC7
CID
Constant H level
IC7
@
Constant H level
ICS
@
Negative pulse
Same as
Mi
(CPU bus)
ICS
@
Negative pulse
Same as
lORQ
(CPU bus)
Output terminals of address decoding circuit
•
ICll
®
Develops negative pulse when I/O address COH to C3H (192 to 195) are accessed.
IC9
@
Develops negative pulse when I/O address C4H (196) is read out.
ICg
QV
Develops negative pulse when data are written on to I/O address C4H (1961.
ICg
Q)
Develops negative pulse when data are written on to I/O address C5H (197).
.
~.
25
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