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• Description of Each Circuit
Each circuit will be described. The logic diagrams used for description are simplified schemata of logic.
1. Reset Circuit
RESET----I
)O----~
To Pia M1
M I - - - - - - '
The circuit is intended to reset PlO by the RESET signal from MZ·80B CPU board. Z-80APIO is reset when
MI
terminal is active for 2 clock cycles or over providing that both
"Fm
and
1U"RO"
signals are not active. The RC
circiut in the diagram is a low pass filter provided for preventing faulty operation
d~e
to noise.
2.
Waiting Circuit
m1
MI---\
IDROW
MI----i
.;xl~--<2
LD
EXWAIT
BU&/> - -
Vcc
The waiting circuit corrects the timing of the interrupt vector transmitting from PlO to CPU in the interrupt ac-
knowledge cycle. Thus, 10RQW develops a signal of reversedlORO and EXWAIT doesn't develop pulse in other
cycle than the interrupt acknowledge cycle.
This waiting circuit does not correct the timing of the daisy chain. With the delay of the daisy chain, lED look
ahead is carried out on the extension I/O interface of MZ-80B.
The timing chart in the interrupt acknowledge cycle is illustrated below.
Lalt M cycle
I
Interrupt
detection
-----""\ Ir---
---- --41-
~
--
T2
Tw·
.
.
Wait line
.
detection
I nterrupt vector
T ' i
Tw
input
c----,
EXWAIT
,)pROW
________________________________
----~I
\'----
21
c
(
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