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3. Addre •• Decoding Logic
A,
A.
-r---i.._
As
A.
- - < I
A, - - < 4
,--_ _ Decoded output of
COH
to
C7H
to
PlO
~
(COH-C3H)
C
B
Ao
~A~~~----.
W,
(C5H)'
W
I
(C4H)
RI
(C4H)
• ICg
AH·iX0303PAZZ
SN74LS138N
Pin Assignment (Top View)
Vcc
YO
Y1
("lA •
V2
DATA
ENABLE
G28
5
Y3
OUTPUT
~1
6
V4
OUTPUT
V7
VS
V6
The address decoding logic forms ~ signal of PlO and A
I,
W
I
and W
2
signals of H IC from the signals Ao to
A" AD, WA and 10POW. The decoded output of COH to C7H is used by the data buffer control logic.
4. Data Buffer Control Logic
IEI - - - - I
IEO
-----0
MY
- - - - 0
RD
- - - d
Decoded output of
COH
to
C7H
IOROW
(lORO)
p----
To No. 1 pin of IC6
(LS24S1
The data buffer control logic ,regulates the buffer connecting the CPU data bus line and the bus lines of PlO and
HIC. CPU reads data when the No. 1 pin of ICS is in low level. CPU reads data when the 10 addresses of COH
to C7H are input to CPU and CPU reads the interrupt vector from PlO in the mode 2 interrupt acknowledge cycle.
,
5. Timing Circuit
a
B
5/ols
The timing circuit forms pulses of about 500J,Jsec. and about 5J,Jsec. 500J,Jsec. determines the time for receiving
one command when the ATN signal is received in the slave mode and 5J,Jsec. determines the time from trans·
mitting data on to the GP·IB data bus to outputting DAV. It is so designed that 500J,Jsec. pulse is not generated
untillEI becomes high level, by considering the disposition of ATN by interrupt.
27
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