Advertisement
I
MZ-SBI04 DESCRIPTION OF CIRCUIT
: . . J
r--
• Block Diagram
MZ·80B
bus line
This interface circuit consists of a hybrid le (H0001 PAl for GP·IB, Z·80AP10 and various logics to connect them
to the extension I/O of MZ·80B.
Some of included logics are a waiting logic and a data buffer control logic so that the mode 2 interrupt of Z·80A
can be utilized by Z·80API0.
Data bus
1 -
lE
lE
M
A
0 -
1----
0 -
A
7
8
0
I
0 -
A
A
W
R _
.
1 - -
M
BUS4>
IORa
EXWAI T
T
lE 0
I
T
M
RESE
- -
8
Buffer control
logic
Address decod·
ing logic
Waiting logic
•
Reset circuit
r---
....
DB7
tU
...
I
...
8
~
DBO
Dltl b
ID
us
8
8
R1
W1
I - -
W2
3
I-
HIC
Hind
07
Mlnlgemlnt
L...,.
I
line
line
GP·IB
sheke
DO
-
-
CE
5
TACS
5
Z·80A
Mlnage
PlO
LACS
line
-
ment
MI
8
CMAC NBA
Command
ACCS
NBAW
-
INT
reed
IEO
l
-
IEI
iEi-
Timing circuit
MZ-8BI04 Block Diagram
.
..
~--------------------------------------------------------------------------------------~
19
Advertisement
