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Note:
If a quadword access is specified for the configuration cycle, then the
least significant bit of the register number field (such as ad<2>) must be
zero. Quadword transactions must access quadword aligned registers.
If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is,
a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-to-
PCI bridge. This cycle is accepted by the PCI-to-PCI bridge for propagation to its
secondary PCI bus. During this cycle, <23:16> selects a unique bus number, and
address <15:8> selects a device on that bus (typically decoded by the PCI-to-PCI
bridge to generate the secondary PCI address pattern for IDSEL). In addition,
address <7:2> selects a Dword (longword) in the device's configuration space.
Table 1–10 contains the PCI configuration space read/write encodings.
Table 1–10 PCI Configuration Space Read/Write Encodings
Size
addr_h<4:3>
Byte
00
3
Word
01
Tribyte
10
Longword
11
Quadword
11
1
Byte enable set to 0 indicates that byte lane carries meaningful data
2
.
A<7> = addr_h<7>
3
Missing entries (for example, word size with addr_h<6:5> = 11) generate UNPREDICTABLE results.
Each PCI-to-PCI bridge can be configured via PCI configuration cycles on its primary
PCI interface. Configuration parameters in the PCI-to-PCI bridge will identify the bus
number for its secondary PCI interface and a range of bus numbers that may exist hier-
Byte Offset
21164
addr_h
Instruction
<6:5>
Allowed
00
01
10
LDL,STL
11
00
01
LDL,STL
10
00
01
LDL,STL
00
LDL,STL
11
LDQ,STQ
PCI Configuration Space
PCI Byte
1
ad<2:0>
Enable
2
A<7>
,00
1110
A<7>,00
1101
A<7>,00
1011
A<7>,00
0111
A<7>,00
1100
A<7>,00
1001
A<7>,00
0011
A<7>,00
1000
A<7>,00
0001
A<7>,00
0000
000
0000
.
System Address Space
Data-In Register
Byte Lanes
63.....32 31.......0
OOOX
OOXO
OXOO
XOOO
OOXX
OXXO
XXOO
OXXX
XXXO
XXXX
XXXX XXXX
A–29
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