Pci Memory Sparse-Space Read/Write Encodings - Samsung AlphaPC 164UX Technical Reference Manual

PCI Sparse Memory Space
Table 1–6 defines the low-order PCI sparse memory address bits. Signals
addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte
enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quad-
word PCI address and are sent out on ad<25:3>.
Table 1–6 PCI Memory Sparse-Space Read/Write Encodings
Size
addr_h<4:3>
Byte 00
4
Word 01
Tribyte 10
Longword 11
Quadword 11
1
Byte enable set to 0 indicates that byte lane carries meaningful data
2
.
A<7> = addr_h<7>
3
In PCI sparse memory space, ad<1:0> is always zero.
4
Missing entries (for example, word size with 21164 address = 11) enjoy UNPREDICTABLE results.
System Address Space
A–20
Byte Offset 21164
addr_h Instruction
<6:5> Allowed
00
01
10 LDL,STL
11
00
01 LDL,STL
10
00
01 LDL,STL
00 LDL,STL
11 LDQ,STQ
Data-In Register
PCI Byte Byte Lanes
1
ad<2:0> Enable 63.....32 31.......0
2 3
A<7> ,00 1110
A<7>,00 1101
A<7>,00 1011
A<7>,00 0111
A<7>,00 1100
A<7>,00 1001
A<7>,00 0011
A<7>,00 1000
A<7>,00 0001
A<7>,00 0000
000 0000
.
OOOX
OOXO
OXOO
XOOO
OOXX
OXXO
XXOO
OXXX
XXXO
XXXX
XXXX XXXX