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PCI Configuration Space
Peripherals are selected during a PCI configuration cycle if the following three con-
ditions are met:
1. Their IDSEL pin is asserted.
2. The PCI bus command indicates a configuration read or write.
3. Address bits <1:0> are 00.
Address bits <7:2> select a Dword (longword) register in the peripheral's 256-byte
configuration address space. Transactions can use byte masks.
Peripherals that integrate multiple functional units (for example, SCSI and Ethernet)
can provide configuration space for each function. Address bits <10:8> can be
decoded by the peripheral to select one of eight functional units.
Signals ad<31:11> are available to generate the IDSEL bits (note that IDSEL bits
behind a PCI-to-PCI bridge are determined from the device field encoding of a type
1 access). The IDSEL pin of each device is connected to a unique PCI address bit
from ad<31:11>. The binary value of addr_h<20:16> is used to select which
ad<31:11> is asserted, as shown in Table A–9.
Table A–9 CPU Address to IDSEL Conversion
CPU Address <20:16>
00000
00001
00010
00011
.....
.....
10011
10100
10101
.....
.....
11111
System Address Space
A–28
ad<31:11> – IDSEL
0000 0000 0000 0000 0000 1
0000 0000 0000 0000 0001 0
0000 0000 0000 0000 0010 0
0000 0000 0000 0000 0100 0
.... .... .... .... .... .
.... .... .... .... .... .
0100 0000 0000 0000 0000 0
1000 0000 0000 0000 0000 0
0000 0000 0000 0000 0000 0
...(No device selected)
—
0000 0000 0000 0000 0000 0
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