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AlphaPC 164UX Bcache Interface
3.1 AlphaPC 164UX Bcache Interface
The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array
(see Figure 3–1). The data bus (pdata<127:0>), check bus (pecc<15:0>),
p_tag_dirty and p_tag_ctl_par signals are shared with the system interface.
Figure 3–1 AlphaPC 164UX L3 Bcache Array
21164
Microprocessor
tag_data<38:32>
tag_data<31:20>
tag_data_par
tag_ctl_par
tag_valid
tag_dirty
pdata<127:0>
pecc<15:0>
untermstclk1
idle_bc
pc164ux.1-2
The Bcache is a 2MB or 4MB, direct-mapped, synchronous SRAM (SSRAM)
with a 128-bit data path. It is populated with a quantity of eight 128K
256K x 18 SSRAMs for data store, and one 64K
In most cases, wave-pipelined accesses can decrease the cache loop times by
one CPU cycle. The Bcache supports 64-byte transfers to and from memory.
3.2 Digital Semiconductor 21174 Core Logic Chip
The 21174 core logic chip provides a cost-competitive solution for designers using the
21164 microprocessor to develop uniprocessor systems. The chip provides a 128-bit
memory interface and a PCI I/O interface, and includes the Digital Semiconductor
21174-CA chip packaged in a 474-pin plastic ball grid array (PBGA).
Functional Description
3–2
CDC2351
(From 21174 Chip)
index<21:4>
*cacheoe
*cachewe
*tag_ram_oe
*tag_ram_we
index<21:6>
Tag
Array
stclk<9:1>
pc164ux.4
18 SSRAM for the tag store.
X
Bcache
SRAM
Data
Array
pc164ux.5-6
18 or
X
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