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1.8 PCI Sparse I/O Space
The PCI sparse I/O space is divided into two regions — region A and region B.
Region A addresses the lower 32MB of PCI I/O space and is never relocated. This
region will be used to address the (E)ISA devices. Region B is used to address a fur-
ther 32MB of PCI I/O space and is relocatable using the HAE_IO register.
A.8.1 Hardware Extension Register (HAE_IO)
In sparse space, the 21164 address bits <7:3> are used to encode byte enable bits,
size bits, and the low-order ad<2:0>. This means that there are now five fewer
address bits available to generate the PCI physical address.
The system provides two PCI sparse I/O space regions and allows one region to be
relocated by way of bits in the HAE_IO register.
A.8.2 PCI Sparse I/O Space Access Operation
The PCI sparse I/O space is located in the range 85.8000.0000 to 85.FFFF.FFFF.
This space has characteristics similar to the PCI sparse memory space. This 2GB
21164 address segment maps to two 32MB regions of PCI I/O address space. A read
or write transaction to this space causes a PCI I/O read or write command. The high-
order PCI address bits are handled as follows:
•
Region A: This region has addr_h<34:30> = 10110 and addresses the lower
32MB of PCI sparse I/O space. Signals ad<31:25> are asserted at zero by the
hardware (see Figure 1–12). Region A is used to address (E)ISA address space
(the EISA 64KB I/O space cannot be relocated). Figure 1–12 shows PCI sparse
I/O space address translation in Region A.
•
Region B: This region has addr_h<34:30> = 10111 and addresses a relocatable
32MB of PCI sparse I/O space. This 32MB segment is relocated by assigning
ad<31:25> to equal HAE_IO<31:25>. Figure 1–13 shows PCI sparse I/O space
address translation in Region B.
The remainder of the PCI I/O address is formed in the same way for both regions:
•
ad<24:3> are derived from addr_h<29:8>.
•
ad<2:0> are defined in Table 1–8.
PCI Sparse I/O Space
System Address Space
A–23
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