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Digital Semiconductor 21174 Core Logic Chip
•
Generates the clocks, row, and column addresses for the SDRAM DIMMs, as
well as all of the memory control signals (*RAS,*CAS, *WE). All of the
required SDRAM refresh control is contained in the 21174.
•
Provides all the logic to map 21164 noncacheable addresses to PCI address
space, as well as all the translation logic to map PCI DMA addresses to system
memory.
Two DMA conversion methods are supported:
•
Direct mapping, in which a base offset is concatenated with the PCI address.
•
Scatter-gather mapping, which maps an 8KB PCI page to any 8KB memory
page. The 21174 contains an eight-entry scatter-gather translation lookaside
buffer (TLB), where each entry holds four consecutive page table entries (PTEs).
Refer to Appendix A for additional details on PCI and DMA address mapping.
3.2.2 Main Memory Interface
Five Data Switches provide the interface between the 21164/L3 cache (pdata<127:0>,
pecc<15:0>) and the memory/21174 (mdata<127:>, mecc<15:0>). The AlphaPC
164UX supports six168-pin unbuffered 72-bit SDRAM DIMM modules. Quadword
ECC is supported on the SDRAM and CPU buses. Even parity is generated on the PCI
bus.
The AlphaPC 164UX supports a maximum of 1536MB of main memory. The mem-
ory is organized as three banks. Table 1–1 lists total memory options along with the
corresponding DIMM sizes required. All CPU cacheable memory accesses and PCI
DMA accesses are controlled and routed to main memory by the 21174 core logic
chip.
The AlphaPC 164UX implements the alternate memory mode for SDRAM RAS
and CAS control signals. Alternate memory mode is explained in the Digital
Semiconductor 21174 Core Logic Chip Technical Reference Manual.
3.2.3 PCI Devices
The AlphaPC 164UX uses the PCI bus as the main I/O bus for the majority of
peripheral functions. As Figure 3–3 shows, the board implements the ISA bus as an
expansion bus for system support functions and for relatively slow peripheral
devices.
Functional Description
3–4
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