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Scatter-Gather TLB
mapping. Both paths are indicated — the right side shows the path for a TLB hit,
while the left side shows the path for a TLB miss. The scatter-gather TLB is shown
in a slightly simplified, but functionally equivalent form.
A.15.1 Scatter-Gather TLB Hit Process
The process for a scatter-gather TLB hit is as follows:
1. The window compare logic determines if the PCI address has hit in one of the
four windows, and the PCI_BASE<SG> bit determines if the scatter-gather path
should be taken. If window 3 has DAC-mode enabled, and the PCI cycle is a
DAC cycle, then a further comparison is made between the high-order PCI bits
and the PCI DAC BASE register.
2. PCI address ad<31:13> is sent to the TLB associative tag together with the
DAC hit indication. If ad<31:13> and the DAC bits match in the TLB, then
the corresponding 8KB 21164 page address is read out of the TLB. If this entry
is valid, then a TLB hit has occurred and this page address is concatenated
with ad<12:2> to form the physical memory address. If the data entry is
invalid, or if the TAG compare failed, then a TLB miss occurs.
A.15.2 Scatter-Gather TLB Miss Process
The process for a scatter-gather TLB miss is as follows:
1. The relevant bits of the PCI address (as determined by the window mask regis-
ter) are concatenated with the relevant translated base register bits to form the
address used to access the scatter-gather map entry (PTE) from a table located in
main memory.
2. Bits <20:1> of the map entry (PTE from memory) are used to generate the phys-
ical page address, which is appended to the page offset to generate the physical
memory address. The TLB is also updated at this point, using a round-robin
algorithm, with the four PTE entries that correspond to the 32KB PCI page
address that first missed the TLB. The tag portion of the TLB is loaded with this
PCI page address, and the DAC bit is set if this PCI cycle is a DAC cycle.
3. If the requested PTE is marked invalid (bit 0 is clear), then a TLB invalid entry
exception is taken.
System Address Space
A–42
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