Blanking And Spot Killer - NEC MultiSync V720 Service Manual

8.

Blanking and spot killer

Circuit Diagram
R3
V-SYNC
R1
D1
V-OUT
C2
Description of the circuit:
1) The vertical blanking circuit completes by Q1, Q2, Q3 and peripheral circuit.
The vertical sync pulse applied to R3, R12 connected to Q5 base. Q5 is invert amplifier, then
mixer with Q1 base together for compensate vertical retrace time of the blanking pulse.
2) The vertical amplifier output waveform through D1, C2, R1, R2 make waveform forming and
clamp. Then applied to Q1 base, the vertical blanking amplifier of the Q1, the output connected
to buffer Q2, through C3 coupling to G1 control circuit. D4, D5 for over voltage protect.
3) The Q6 is spot killer protect circuit, in normal power on stage.
V1 = V2 and ZD1, so Q6 off. The CRT G1 voltage is fixed at –45 ~
pulse 12Vpp VG1 =
When power off the voltage V1 > V2, then Q6 turn on pulling VG1 to –180V to protect CRT.
4) When Mute set to lower the Q3 off G1 =
makes active, at power ON/OFF and when mode change stage.
5) Q4 bias set up by MCU to control the V
Test points for maintenance:
1) Check D1, R3 and Q1 collector
2) G1 voltage control range=
G1 off momentary voltage ¡Ü
Q5
R6
R12
Q1
R2 R5
− ×
(V R11) / (R10 + R11), (V = V1
− −
45 ~ 67VDC
−
180VAC
¡Ü
¡Ü
¡Ü ¡Ü
R4
Q2
D4
R11
C3
V2
D5
ZD1
C5
+
−
V3).
−
180V screen cut off no picture display, this mute circuit
bias of Q3, then control G1 voltage output.
CE
64
VCC
G1
R7
D6
R10
Q4
Q3
Q6
V3
VE
V1
C4
−
67V with vertical blanking
DC
MUTE
R8
BRIGHT
CONTER
R9