NEC MultiSync V720 Service Manual page 57

(5) Data bytes transmit/receive
If the RW bit is "1", the shift register will load data from the data buffer (REG#18H) before the data byte
is transmitted and shift out data to the SDA pin before the rising edge of the SCL clock.
If the RW bit is "0", the shift register will shift in data on the rising edge of the SCL clock and the whole
data byte is latched to the data buffer (REG#18H).
(6) Handshaking procedure
The handshaking is done on the byte level. The DDC interface will hold the SCL pin low after the ac-
knowledge bit automatically. The bus master will be forced to wait until the WT6018 is ready for the next
byte transfer. To release the SCL pin, write REG#19H will release clear the wait state.
(7) Interrupt INT0
The DDC interface interrupt is enabled by setting the IEN_D bit in the REG#1AH.
Interrupt INT0 occurs when:
- Transmit buffer empty in DDC1 state.
The INT0 occurs when the shift register load data from data buffer.
Write REG#18H will clear the transmit buffer empty condition.
- Acknowledge is detected in DDC2B state.
The INT0 occurs on the falling edge of the SCL clock after the acknowledge had been detected.
The SCL pin will be pulled low to force the bus master to wait until the service routine write
REG#19H.
- STOP condition occurs in DDC2B mode
Address R/W Initial
0018H R/W
0019H R
0019H W
Bit Name
DDC2B
ADDR
RW
START
STOP
ENACK
A6, A5, ... , A0
D7, D6, ... , D0
Bit7 Bit6
FFH D7 D6
40H DDC2B ADDR
A0H A6 A5
Bit value = "1"
DDC2B state.
Received address equals to the address
in REG#19H(W).
Received R/W bit is '1'
START condition is detected.
STOP condition is detected.
Enable acknowledge.
7-bit slave address
Data to be transmitted or received data.
Bit5 Bit4 Bit3
D5 D4 D3
R/W START STOP
A4 A3 A2
DDC1 state.
Received address equals to '1010000'
Received R/W bit is '0'
No START condition is detected.
No STOP condition is detected.
Disable acknowledge.
54
Bit2 Bit1 Bit0
D2 D1 D0
-- --
A1 A0 ENACK
Bit value = "0"
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