Video Mute And Video Blanking Circuit; Abl Circuit - NEC MultiSync 4FGe Service Manual

3-3. Video Blanking Circuit and Video Mute Circuit
The H blanking pulse is applied to the push pull circuit which is composed of Cl771 and Q772. During the blanking
period this pulse turn on the transistor Ql and the video amplifier at cut-off. The video mute signal is generated at
the CPU (pin @I), when input signal is changed. Q770 is turned on by the video mute signal from the CPU. Then

3-4. ABL Circuit

The maximum average current flowing through the CRT is' controlled to under 450uA by limiting the video Vp-p
swing. The voltage of CN-J3 is clamped at 12.6V by 0720 when the anode current is 450uA or less. If the anode
current exceeds 450uA, the voltage of CN-J3 drops to less than 12.6V due to the voltage drop of FE34 and R535.
This drives Q722 and Q721 to decrease the collector potential of Q721, and the gain of IC702 is decrease.
A8 VIDEO MUTE
0
0772
J4
BLANKING PULSE
(Fig 3-3-l) Video Blanking and Mute Circuit
0
R534
(Fig 3-4-l) ABL Circuit
CN-J3
54