Panasonic EURO 4 Chassis Technical Manual page 49

RGB signals are then output as 10 bits of
information. The same multipliers are also used to
implement a software beam current control which
will be mentioned later.
The digitised RGB signals, along with the display
and clock control data are synchronised to the
Horizontal flyback pulse with in the Display buffer.
The display clock is fed via a delay phase shift circuit
used to ensure the clock is in synchronisation with
the horizontal flyback pulse input via pin 36 of the
VDP.
Here the Display buffer, is used to adjust any phase
differences between the RGB signals and the
Horizontal flyback signal, before feeding the RGB
signal to the final processing stage which consists of
D/A converters, providing the analogue output
signals.
17.8. Analogue Back End
The digital 10 bit RGB signal is fed from the Display
processor, previously explained, and input to the
Analogue Back End. Here the digital RGB signal is
converted to analogue RGB, before being output
from the VDP IC601.
The digital RGB signal is converted to analogue
using 3 digital to analogue converters (DAC), with 10
bit resolution, here an analogue brightness value is
added to the RGB signal. The brightness value
having an adjustment range of 40% of the full RGB
range.
The backend also allows the insertion of external
analogue RGB signals from the microprocessor,
which provides text and OSD information, as well
the RGB input via AV1.
The text/OSD information is input to the VDP
via pins 45 (R), 46 (G) and 47 (B) with the fast
blanking pulse input via pin 48. The RGB signal input
via AV1 is fed to IC601 via pins 41 (R), 42 (G) and 43
(B) with the blanking pulse being input via pin 44 .
Also included in the display processor stage of the
VDP IC601
used where the picture does not fill the total area of
the screen (height or width to small). In this case the
area around the picture is surrounded with black
bars. These areas are coloured with the picture
frame generator, by switching over the RGB signal
from the matrix to the signal from the OSD colour
look-up table (CLUT).
The video RGB which is fed to the three multipliers
is also fed to the Scan Velocity Modulator (SVM)
circuit, here the RGB input signal is converted to a
luma (Y) signal which is carried out by a simple
matrix. The analogue output signal is generated by
an 8bit D/A converter where the SVM signal is
output via pin 34 of the VDP IC601.
The selected RGB signal is initially fed to a clamping
circuit, where the signal is independently adjusted
for brightness and contrast. The RGB signal is then
inserted into the main RGB signal path under the
control of the fast blanking pulse.
The external RGB fast blanking pulses are used as
signal switching identification. The priority order of
these signals are set by software controlled via the
2
I C bus.
Control of the white drive, brightness and contrast
adjustments that are carried out on the RGB signals,
are performed using the internal Fast processor
(FP).
In the final stages, before the internal and external
analogue RGB signals are output, cutoff and
blanking values are added to the RGB signals.
Cut off is provided by three 9-bit D/A converters,
IC601 with a cut off adjustment range of 60% of the full
scale RGB range.
The RGB signals are then finally output via pins 39
(B), 38 (G), 37 (R) after blanking pulse information is
added.
49
is the picture frame generator, which is
3DQDVRQLF