Panasonic EURO 4 Chassis Technical Manual page 111

Table of Contents

Advertisement

3DQDVRQLF
Chapter
3
2.4.1. Pin Information
:
AVO - pin 29
Input from the VPC IC1501 is the AVO signal which
is used to synchronise the active video signal.
:
HS - pin 30
Horizontal synchronisation signal input from the VPC
IC1501 which is used for synchronisation of internal
processing.
:
SCL - pin 31
This is the serial clock input which is part of the I
1 control line.
67
R
65
ADC
G
63
B
61
FBL
54
Clock
CLK
Buffer
2
C bus
YUV
4:2:2
36-51
Format
Conversion
4:4:4
CT
Matrix
BR
(on/off)
SAT
:
SDA pin 32
This is the serial data input which is part of the I
1 control line.
:
CLK - pin 54
This input provides a 13.5MHz clock which provides
synchronisation and timing of the chrominance and
luminance signals in IC1502.
:
RSTN - pin 55
The reset input which is an active LOW input, is used
to ensure correct operation after a power on. This is
acheived by keeping the CIP IC in a stable condition
during this period.
CIP3250
Soft
Adjustable
Mixer
LPF
4:4:4
28
EURO 4H Supplement
2
Format
Conversion
10-17
20-27
31
2
32
C
I
Interface
C bus
YUV
4:2:2
2
C
I
Bus

Advertisement

Table of Contents
loading

Table of Contents