Panasonic EURO 4 Chassis Technical Manual page 148

Chapter 4
3.2.1. Teletext Operation
To enable teletext processing by the microprocessor
IC1101 a CVBS signal is input via pin 68. Here the
signal is fed to the Teletext (TTX) slicer stage, where
the horizontal and vertical sync. information and TTX
data are extracted from the CVBS signal. To do this
the slicer has an analogue circuit for sync. filtering and
data slicing as well as an analogue PLL used for
system clock generation.
A third PLL is used to shift the system clock for data
sampling of the TTX signal.
Output from the slicer stage the sliced bit stream is fed
to the Acquisition stage where this bit stream is
converted into a byte stream and a framing code
check to identify the TTX signal takes place.
After framing code detection a status word is
generated which is used to identify the type of data
received and the signal quality of the TV channel.
The text data is then fed via the dual port interface to
the buffer, where under the control of the internal CPU
the data is stored in the display RAM until the TTX data
is required.
When the TTX data is requested the information is
read out of the Display RAM via the interface and fed
to the Display Generator.
The display generator then selects the pixel
information from the character ROM and translates it
into RGB values.
The character generator itself includes a character
and control decoder, a RAM interface, RGB and
Blanking signal generators.
To allow the character generator to carry out
processing of the TTX signal, generation of a pixel
clock is required.
This generation of the pixel clock is created internally
by the display timing stage which is fed a horizontal
and vertical sync signal input via pins 46 and 47.
The TTX data which has now been converted to RGB
values are then output from pins 37 (R), 38 (G), 39 (B)
with the blanking signal being output via pin 40. These
signals are then fed to the VDP IC601.
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3DQDVRQLF
EURO 4D Supplement