Sharp CD-MD3000H Service Manual page 95

IC2 VHiTC9490F/-1: Servo/Signal Control (TC9490F) (2/2)
Pin No. Terminal Name
39 AVDD3
40 FMO
41 DMO
42 VSS3
43 VDD3
44 TESIN
45 XVSS3
46 XI
47 XO
48 XVDD3
49 DVSS3
50 RO
51 DVDD3
52 DVR
53 LO
54 DVSS3
55* ZDET
56 VSS5
57-60 BUS0-BUS3
61 BUCK
62 /CCE
63 /RST
64 VDD5
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: AI/F: Analog input/output terminal
3-5I/F: Terminal with a built-in 3-5 interface (5V system input/output terminal)
3I/F: 3V system input/output terminal
Input/Output
— Analog 3.3V power supply terminal.
Output Feed equalizer output terminal.
Output Disc equalizer output terminal.
— Digital GND terminal.
— Digital 3.3V power supply terminal.
Input Test input terminal. Usually "L" fixed.
— GND terminal for system clock oscillation circuit.
Input System clock oscillation circuit input terminal.
Output System clock oscillation circuit output terminal.
— 3.3V power supply terminal for system clock oscillation circuit.
— GND terminal for D/A converter.
Output R channel data normal rotation output terminal.
— 3.3V power supply terminal for D/A converter.
— Reference voltage terminal.
Output L channel data normal rotation output terminal.
— D/A converter section GND terminal.
Output 1-bit D/A converter 0 detection flag output terminal.
— GND terminal for microcomputer interface.
Input/Output Data input/output terminal for microcomputer interface.
Input Clock input terminal for microcomputer interface.
Input Chip enable signal input terminal for microcomputer interface.
In case of "L", BUS3-0 are active.
Input Reset signal input terminal. Reset: "L".
— 5V power supply terminal for microcomputer interface.
48 46 45
47 44
DVSS3
49
Clock
RO
50
generator
DVDD3
51
LPF
DVR
52
1-bit
DAC
LO
53
DVSS3
54
ZDET
55
VSS5
56
BUS0
57
Correction
BUS1
58
circuit
BUS2
59
BUS3
60
Audio output
BUCK
61
circuit
/CCE
62
/RST
63
VDD5
64
1 4
2 3 5
Figure 95 BLOCK DIAGRAM OF IC
Function
43 42
41 40 39 38 37
PWM
Servo control
ROM
Digital equalizer
Address
adjustment circuit
circuit
RAM
CLV
servo
16K RAM
Synchronizing
signal guarantee
EFM demodulation
Digital
out
Sub-code
demodulation
circuit
8 11
6 7 9 10 12
– 95 –
CD-MD3000H/CD-MD3000W
36 35 34 33
32 TEZI
+
TEI
31
D/A
SBAD
30
29
FEI
+
A/D
RFRP
28
RFZI
+ 27
26 RFCT
AVDD3
25
24 RFI
Data
slicer
23 SLCO
22 AVSS3
VCO
21 VCOF
PVREF
20
19 LPFO
PLL
+
TMAX
18 LPFN
17 TMAX
13 14
15 16