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Electrical and Mechanical Specifications
Electrical
SIGNAL
PIN
NAME
LOGIC
1
Vcc
POWER
3
GND
BUS
5
VBB#1/VBAT
7
D3/A19
9
D2/A18
DATA BUS
11
D1/A17
13
D0/A16
15
A7
17
A6
19
A5
ADDRESS
21
A4
BUS
23
A3
25
A2
27
A1
29
A0
31
WR*
33
IORQ*
35
IOEXP*
37
REFRESH*
39
STATUS 1*
CONTROL
41
BUSAK*
BUS
43
INTAK*
45
WAITRQ*
47
SYSRESET*
49
CLOCK*
51
PCO*
AUXILIARY
53
AUX GND
POWER
BUS
55
AUX +V
* Low-level active indicator
Mechanical
Connector Spacing: 5/8" (0625")
Mechanical Dimensions: See Included Drawings
082791
COMPONENT SIDE
SIGNAL
FLOW
DESCRIPTION
In
Logic Power (+5VDC)
In
Logic Ground
In
Logic Bias #1/Bat Pwr
In/Out
In/Out
Data Bus/Address Ext
In/Out
In/Out
Out
Out
Out
Out
Address Bus
Out
Out
Out
Out
Out
Write to Memory or I/O
Out
I/O Address Selection
In/Out
I/O Expansion
Out
Refresh Timing
Out
CPU Status
Out
Bus Acknowledge
Out
Interrupt Acknowledge
In
Wait Request
Out
System Reset
Out
Clock from Processor
Out
Priority Chain Out
In
AUX Ground
In
AuX Positive (+12VDC)
OPERATIONS MANUAL
BP/CX 3-26 CARDCAGES/MOTHERBOARDS
CIRCUIT SIDE
SIGNAL
PIN
SIGNAL NAME
FLOW
2
Vcc
In
4
GND
In
6
VBB#2/DCPD*
In
8
D7/A23
In/Out
10
D6/A22
In/Out
12
D5/A21
In/Out
14
D4/A20
In/Out
16
A15
Out
18
A14
Out
20
A13
Out
22
A12
Out
24
A11
Out
26
A10
Out
28
A9
Out
30
A8
Out
32
RD*
Out
34
MEMRQ*
Out
36
MEMEX*
In/Out
38
MCSYNC*
Out
40
STATUS 0*
Out
42
BUSRQ*
In
44
INTRQ*
In
46
NMIRQ*
In
48
PBRESET*
In
50
CNTRL*
In
52
PCI
In
54
AUX GND
In
56
AUX-V
In
DESCRIPTION
Logic Power (+5VDC)
Logic Ground
Logic Bias #2/Pwr Dwn
Data Bus/Address Ext
Address Bus
Read Memory or I/O
Memory Address Selection
Memory Expansion
CPU Machine Cycle Sync.
CPU Status
Bus Request
Interrupt Request
Nonmaskable Interrupt
Pushbutton Reset
AUX Timing
Priority Chain In
AUX Ground
AUX Negative (-12VDC)
2
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