Intel 740 Design Manual page 41

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INTEL740(TM) GRAPHICS ACCELERATOR FULL FEATURED REFERENCE CARD
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TITLE
COVER SHEET
BLOCK DIAGRAM
INTEL740(TM) GRAPHICS ACCELERATOR (A)
INTEL740(TM) GRAPHICS ACCELERATOR (B)
VOLTAGE REGULATOR
BT829B VIDEO DECODER
BT869 VIDEO ENCODER
VMI VIDEO CONNECTOR
AGP CONNECTOR
VGA CONNECTOR
VMI/DDC/I2C/FANFAIL LEVEL SHIFTER
SO-DIMM
SGRAM
VIDEO CONNECTORS
3 BIOS/FAN CONNECTOR
REVISION HISTORY
2
1
A
B
PAGE
P.1
P.2
P.3
P.4
P.5
P.6
P.7
P.8
P.9
P.10
P.11
P.12
P.13
P.14
P.15
P.16
P.17
B
C
C
D
+12V
+12V = 12V ANALOG UNLESS OTHERWISE SPECIFIED
VCC
VCC = 5V DIGITAL UNLESS OTHERWISE SPECIFIED
VCC3
VCC3 = 3.3V DIGITAL UNLESS OTHERWISE SPECIFIED
VDD VDDQ = 3.3V AGP POWER SUPPLY
VCC_CORE = VOLTAGE SUPPLIED TO THE INTEL740 CHIP CORE
GND = DIGITAL GND
THIS SPECIFICATION IS PROVEDED AS IS WITH NO WARRANTIES
WHATSOVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS
FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO
ANY INTELLECTUAL PRPERTY RIGHTS IS GRANED HEREIN.
INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR
INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF
INFORMATION IN THIS SPECIFICATION. INTEL DOES NOT WARRANT
OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS.
I2C IS A TWO-WIRE COMMUNICATIONS BUS/PROTOCOL DEVELOPED BY
PHILIPS. SMBUS IS A SUBSET OF THE I2C BUS/PROTOCOL AND WAS
DEVELOPED BY INTEL. IMPLEMENTATIONS OF THE I2C BUS/PROTOCAL
OR THE SMBUS BUS/PROTOCOL MAY REQUIRE LICENSES FROM VARIOUS
ENTITIES, INCLUDING PHILIPS ELECTRONICS N.V. AND NORTH
AMERICAN PHILIPS CORPORATION.
*THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR
RESPECTIVE OWNERS.
COPYRIGHT * INTEL CORPORATION 1997
Title
Cover Sheet
Size Document Number
C Intel740(TM) Graphics Accelerator Reference Card
Date: Thursday, April 09, 1998
D
E
4
3
2
1
Rev
2.1
Sheet 1 of 16
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