Four Layer Board Stack-Up - Intel 740 Design Manual

Figure 2-5. Four Layer Board Stack-up
Z = 65 ohms
Z = 65 ohms
Note: Top and bottom routing layers specify 1/2 oz. cu. However, by the time the board is plated, the
traces will end up with about 1 oz. cu. Please check with your fabrication vendor on the exact value
and insure that any signal simulation accounts for this.
Note: Thicker core helps reduce board warpage issues, while thinner prepreg reduces trace impedance.
Additional guidelines on board buildup, placement and layout include:
•
All layers should be cut back from the substrate outer edge by 0.050". A 0.025"-wide strip
should be added to all signal and power layers around the outer edge and tied to the ground
plane.
•
All power and ground traces between vias and pads for all components should be at least as
wide as the component power or ground pad itself.
•
Through-hole vias, unless otherwise noted, are 10 mil drill, 25 mil diameter pad. Via capping
is required. All vias on the secondary side should be covered with solder mask. All vias on the
primary side are to be encroached with solder mask and anti-pad unless board dryness has
been guaranteed.
•
To minimize solder wicking with the BGA, the component side solder mask should be applied
prior to tinning the copper. There should be no surface mount over bare copper (S.M.O.B.C.).
•
The solder mask must cover the trace between the via and pad.
•
The board impedance (Z) should be between 50 and 80 ohms (65 ohms ±20%).
•
FR-4 material should be used for the board fabrication.
•
The ground plane should not be split on the ground plane layer. If a signal must be routed for a
short distance on a power plane, then it should be routed on a VCC plane, not the ground
plane.
•
Keep vias for decoupling capacitors as close to the capacitor pads as possible.
•
Keep isolated power planes as close as possible to each other. This will minimize impedance
mismatch at the split.
•
All decoupling capacitors should be tied to the ground plane by a trace at least as wide as the
via ring to the plane.
Intel740™ Graphics Accelerator Design Guide
6 mils
PREPREG
50 mils
CORE
6 mils
PREPREG
Addin Card Design
Primary Signal Layer (1/2 oz. cu.)
Ground Plane (1 oz. cu.)
Power Plane (1 oz. cu)
Secondary Signal Layer (1/2 oz. cu)
Total board width = 62
+
.6 mils
2-7