SanDisk CompactFlash Product Manual page 21

Signal Name Dir.
-IOWR
(PC Card Memory Mode)
-IOWR
(PC Card I/O Mode)
-IOWR
(True IDE Mode)
-OE
(PC Card Memory Mode)
-OE
(PC Card I/O Mode)
-ATA SEL
(True IDE Mode)
RDY/-BSY O
(PC Card Memory Mode)
-IREQ
( PC Card I/O Mode)
INTRQ
(True IDE Mode)
-REG
(PC Card Memory Mode)
Attribute Memory Select
-REG
(PC Card I/O Mode)
-REG
(True IDE Mode)
RESET
(PC Card Memory Mode)
RESET
(PC Card I/O Mode)
-RESET
(True IDE Mode)
VCC --
(PC Card Memory Mode)
VCC
(PC Card I/O Mode)
VCC
(True IDE Mode)
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CompactFlash Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
Pin
I 35 This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the
CompactFlash controller registers when the card is configured to use the I/O interface.
The clocking will occur on the negative to positive edge of the signal (trailing edge).
In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
I 9 This is an Output Enable strobe generated by the host interface. It is used to read
data from the CompactFlash Card in Memory Mode and to read the CIS and
configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and configuration registers.
To enable True IDE Mode this input should be grounded by the host.
37 In Memory Mode this signal is set high when the CompactFlash Card is ready to
accept a new data transfer operation and held low when the card is busy. The Host
memory card socket must provide a pull-up resistor.
At power up and at Reset, the RDY/-BSY signal is held low (busy) u ntil the
CompactFlash Card has completed its power up or reset function. No access of any
type should be made to the CompactFlash Card during this time. The RDY/ -BSY
signal is held high (disabled from being busy) whenever the following condition is true:
The CompactFlash Card has been powered up with +RESET continuously
disconnected or asserted.
I/O Operation—After the CompactFlash Card has been configured for I/O operation,
this signal is used as -Interrupt Request. This line is strobed low to generate a pulse
mode interrupt or held low for a level mode interrupt.
In True IDE Mode, this signal is the active high Interrupt Request to the host.
I 44
This signal is used during Memory Cycles to distinguish between Common Memory
and Register (Attribute) Memory accesses. High for Common Memory, Low for
Attribute Memory.
The signal must also be active (low) during I/O Cycles when the I/O address is on the
Bus.
In True IDE Mode this input signal is not used and should be connected to VCC by the
host.
I 41
When the pin is high, this signal resets the CompactFlash Card. The card is Rese t
only at power up if this pin is left high or open from power-up. The card is also reset
when the Soft Reset bit in the Card Configuration Option Register is set.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode this input pin is the active low hardware reset from the host.
13, 38 +5 V, +3.3 V power.
This signal is the same for all modes.
This signal is the same for all modes.
CompactFlash Memory Card Interface Description
Description
3-5