Chipset Features Setup Menu; Dram Timing; System Bios Cacheable; Video Bios Cacheable - BCM FR550 User Manual

Chipset Features Setup Menu

4.5

DRAM Timing

System BIOS Cacheable

Video BIOS Cacheable

8 bit I/O Recovery Time
16 bit I/O Recovery Time
Memory Hole At 15M-16M
4.5.1 DRAM Timing
The value in this field depends on performance parameters of the installed memory chips
(DRAM). Do not change the value from the factory setting unless you install new memory
that has a different performance rating than the original DRAMs.
4.5.2 System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result.
4.5.3 Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7FFFh, resulting in
better video performance. However, if any program writes to this memory area, a system error
may result.
4.5.4 8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-originated I/O cycles to the
ISA bus. This delay takes place because the PCI bus is so much faster than the ISA bus. These
two fields let you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
4.5.5 Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements.
ROM PCI/ISA BIOS (2A59IB3G)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: 70ns
: Disabled
Disabled
:
: 1
1
:
: Disabled

ESC : Quit
F1 : Help
F5 : Old Values
F7 : Load Setup Defaults
FR550
↑ ↓ → ← : Select Item
PU/PD/+/- : Modify
(Shift)F2 : Color
Figure 4
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