Cpu Port Allocation - Icom IC-E92D Service Manual

4-4 CPU PORT ALLOCATION

LINE
NAME
POWER [POWER] key input. (Pull-up).
PKEY [PWR] key input (Pull-up).
DICK [DIAL] input(Phase A).
DIUD [DIAL] input(Phase B).
PTT [PTT] key input (Pull-down).
SQL [SQL] key input (Pull-up).
I0–I3 Initial matrix ports.
Key detect signal.
KR0–KR4
(Pushed bottom is detected according to the input voltage.)
KS0–KS3 Key matrix ports.
ESIO Serial data to the EEPROM.
ECK Clock to the EEPROM.
TXC T6 line regulator (M: Q650–652) control signal.
BLED [BUSY] LED driver (L: Q201) control signal.
LIGHT LCD/Key backlight driver (L: Q202) control signal.
LCDDT Serial data to the LCD driver (L: DS1).
LCDCS Chip select signal to the LCD driver (L: DS1).
LCDCK Clock to the LCD driver (L: DS1).
LCDRS Strobe signal to the LCD driver (L: DS1).
LCDRES Reset signal to the LCD driver (L: DS1).
AMBEC DSP IC power line regulator (L:IC508) control signal.
DVC Liner CODEC IC power line regulator (L: Q503,504) control signal.
TX232 RS-232 data (TXD).
RX232 RS-232 data (RXD).
TXCK TX clock to the modem (L: IC501).
TXDT TX data to the modem (L: IC501).
RXCK RX clock to the modem (L: IC501).
RXDT RX data to the modem (L: IC501).
ACQ ACQ signal to the modem (L: IC501).
DCEL DCEL signal to the modem (L: IC501).
Reset signal to the liner CODEC IC and DSP CODEC IC (L: IC503 and
AMBERES
IC506).
AMBECLK AMBE clock signal to the DSP CODEC IC (L: IC506).
AMBESTB AMBE strobe signal to the DSP CODEC IC (L: IC506).
AMBETXD AMBE TX data to the DSP CODEC IC (L: IC506).
AMBERXD AMBE RX data to the DSP CODEC IC (L: IC506).
AMBEEPR AMBE EPR signal to the DSP CODEC IC (L: IC506).
CLSFT Clock frequency shift signal to the clock oscillator (L:X1, D13).
DICK2 [DIAL] (VR) input (Phase A).
DIUD2 [DIAL] (VR) input (Phase B).
CHGC Charging control signal to the charge circuit (L:Q150–153, D150, 151)
CHGH Charging current control signal to the charging controller (L: Q150, 152).
CPUHV Externalpower supply detection.
AFON Control signal to the AF power AMP controller (L: Q400, 401).
BATT Power supply select signal to the power supply selector (L: IC50, Q53).
SPSW Speaker select signal to the Internal speaker SW (L: Q402–405).
ANOIS Noise detect signal from the A BAND IF IC (M: IC100).
BNOIS Noise detect signal from the B-AND IF IC (M: IC200).
Common clock signal to the the PLL ICs and DAC (LMX2313/
CK
ME15E03SL/M62352AGP).
Common serial data to the PLL ICs and DAC (LMX2313/ME15E03SL/
DATA
M62352AGP).
DESCRIPTION
4 - 7
IN/OUT STATUS
IN L
IN L The key is pushed
IN –
IN –
IN H The key is pushed
IN L The key is pushed
IN –
IN –
OUT –
IN/OUT –
OUT –
OUT H While transmitting.
OUT H RX(Squelch open)
OUT L Lights ON.
OUT –
OUT –
OUT –
OUT –
OUT –
OUT H In DV mode operation.
OUT H In DV mode operation.
OUT –
IN –
IN –
OUT –
IN –
IN –
OUT H Synchronized
OUT H Synchronized
OUT –
OUT –
OUT –
OUT –
IN –
IN –
OUT H
IN –
IN –
OUT H While charging.
OUT H Charging current increase.
E x t e r n a l p o w e r s u p p l y i s
IN L
connected.
AF power AMP (L: IC400) is
OUT H
activated (Squelch open).
H= Operated by the battery pack.
OUT H/L L= O p e ra t e d by a n ex t e r n a l
power source.
OUT –
IN –
IN –
OUT –
OUT –
CONDITION
–
–
–
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–
–
–
–
–
–
–
–
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–
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