Power Up Reset Timing - Asus P552W Manual

The baseband processor must write a logic 1 to a dedicated I2C
watchdog register bit during the next 8 s period. This will
move the DA9035 into the ACTIVE mode, and start the continuous
watchdog monitoring circuit. Failure to issue the initial watchdog
write will result in shut down of the DA9035 to the power-down state.
Once in the ACTIVE state, the EXT_WAKEUP signal will be
asserted while the nONKEY, nEXTON or VCHG_DETECT are
asserted (after de-bouncing), otherwise it is held low.
All I/Os of the DA9035, connected to the host processor will be
released at the end of the 32 ms countdown.

1.2.4 POWER UP RESET TIMING

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GTC ■ Service Manual
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