Model 2Xx Servers; Dedicated Server For Domino - IBM 170 Servers Manual

Model
830-2402 (1534)
830-2402 (1535)
830-2402 (1536)
830-2403 (1531)
830-2403 (1532)
830-2403 (1533)
830-2403 (1534)
830-2403 (1535)
830-2403 (1536)
830-2403 (1537)
840-2418 (1540)
840-2418 (1541)
840-2418 (1542)
840-2418 (1543)
840-2418 (1544)
840-2418 (1545)
840-2418 (1546)
840-2420 (1540)
840-2420 (1541)
840-2420 (1542)
840-2420 (1543)
840-2420 (1544)
840-2420 (1545)
840-2420 (1546)
840-2420 (1547)
C.11.2 Model 2xx Servers
Table C.11.2.1 Model 2xx Servers
Model
250-2295
250-2296
270-2248 (1517)
270-2250 (1516)
270-2250 (1518)
270-2252 (1516)
270-2252 (1519)
270-2253 (1516)
270-2253 (1520)
C.11.3 Dedicated Server for Domino
Table C.11.3.1 Dedicated Server for Domino
Chip Speed
Model
820-2425
820-2426
820-2427
270-2422
270-2423
270-2424
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
Chip Speed
MHz
540
540
540
540
540
540
540
540
540
540
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
Chip Speed
MHz
200
200
400
400
400
450
450
450
450
L2 cache
CPUs
MHz per CPU
450 2 MB
500 4 MB
500 4 MB
400 n/a
450 2 MB
450 4 MB
Appendix C CPW, CIW and MCU for System i Platform
L2 cache
CPUs
per CPU
4 MB 4
4 MB 4
4 MB 4
4 MB 8
4 MB 8
4 MB 8
4 MB 8
4 MB 8
4 MB 8
4 MB 8
8 MB 12
8 MB 12
8 MB 12
8 MB 12
8 MB 12
8 MB 12
8 MB 12
8 MB 24
8 MB 24
8 MB 24
8 MB 24
8 MB 24
8 MB 24
8 MB 24
8 MB 24
L2 cache
CPUs
per CPU
n/a 1
n/a 1
n/a 1
n/a 1
n/a 1
2 MB 1
1
2 MB
4 MB 2
4 MB 2
Non Domino
CPW
1 100
2 200
4
300
1 50
1
100
2
200
Processor CPW Interactive CPW
4200 560
4200 1050
4200 2000
7350
7350 120
7350 240
7350 560
7350 1050
7350 2000
7350 4550
10000 120
10000 240
10000 560
10000 1050
10000 2000
10000 4550
10000 10000
16500 120
16500 240
16500 560
16500 1050
16500 2000
16500 4550
16500 10000
16500 16500
Processor CPW Interactive CPW
50
75
150
370
370
950
950
2000
2000
Interactive CPW
0
0
0
0
0
0
70
15
20
25
0
30
0
50
0
70
360