V5R3 Additions (May, July, August, October 2004, July 2005); Ibm ~ ® I5 Servers - IBM 170 Servers Manual

Table C.6.1.1. System i models
Edition
Accelerator
Model
2
Feature
Feature
(5)
9406-520 7373 NA
9406-520 7734 NA
Value
9406-520 7352 7357
9406-520 7350 7355
Express
9405-520 7152 NA
9405-520 7144 NA
9405-520 7143 7354
9405-520 7148 7687
9405-520 7156 7353
9405-520 7142 7682
9405-520 7141 7681
9405-520 7140 7680
*Note: 1. These models share L2 and L3 cache between two processor cores.
2. This is the Edition Feature for the model. This is the feature displayed when you display the
system value QPRCFEAT.
3. CPU Range - entry model is a partial processor model, offering multiple price/performance
points for the entry market.
4. Capacity Backup model.
5. High Availability model.
6. Domino edition.
7. The MCU rating is a projected value.
8. The 64-way CPW value is reflects two 32-way partitions.
9. These models are accelerator models. The base CPW or MCU value is the capacity with the
default processor feature. The max CPW or MCU value is the capacity when
purchasing the accelerator processor feature.
10. Collaboration Edition. (Announced May 9, 2006)
11. User based pricing models.
12. These values listed are unconstrained CPW or MCU values (there is sufficient I/O such that
the processor would be the first constrained resource). The I/O constrained CPW value
for an 8-disk configuration is approximately 800 CPW (100 CPW per disk).
NR - Not Recommended: the 600 CPW processor offering is not recommended for Domino.
C.7 V5R3 Additions (May, July, August, October 2004, July 2005)
New for this release is the eServer i5 servers which provide a significant performance improvement when
compared to iSeries model 8xx servers.
IBM ~
C.7.1
®
Table C.7.1.1. ~® i5 Servers
Chip Speed
Model
MHz
595-0952 (7485) 1650
595-0952 (7484) 1650
595-0947 (7499) 1650
595-0947 (7498) 1650
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
L2/L3 cache
Chip Speed
MHz
per CPU
1900 1.9/36MB
1900 1.9/36MB
1900 1.9/36MB
1900 1.9MB/NA
1900 1.9/36MB
1900 1.9/36MB
1900 1.9/36MB
1900 1.9/36MB
1900 1.9/NA
1900 1.9MB/NA
1900 1.9MB/NA
1900 1.9MB/NA
i5
Servers
L3 cache
L2 cache
(
(1) per CPU
per CPU
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
Appendix C CPW, CIW and MCU for System i Platform
CPU Processor
(1)
Range CPW
(3) 1200
1
(3) 1200
1
(3)
1 1200-3800
(3)
1 600-3100
1 3800
3800
1
(3)
1 1200-3800
(3)
1 1200-3800
(3)
1 600-3100
(3)
1 600-3100
(3)
1 600-3100
(3)
1 600-3100
CPU Processor
2)
Range CPW
)
86000-165000
(8
32 - 64
)
86000-165000
(8
32 - 64
16 - 32 46000-85000
16 - 32 46000-85000
5250 OLTP
MCU
CPW
1200 2600
1200 2600
9
60 2600 - 8200
9
30 NR - 6600
60 8200
60 8200
9
60
2600 - 8200
9
60
2600 - 8200
9 30
NR - 6600
9
30
NR - 6600
9
30
NR - 6600
9 30
NR - 6600
5250 OLTP
MCU
CPW
(7)
12000-165000 196000 -375000
(7)
0 196000 -375000
12000-85000 105000 -194000
0 105000 -194000
(9)
(9)
(9)
(9)
(9)
(9)
(7)
(7)
(7)
(7)
350