IBM 170 Servers Manual page 351

Table C.7.1.1. ~® i5 Servers
Chip Speed
Model
MHz
595-0946 (7497) 1650
595-0946 (7496) 1650
570-0926 (7476) 1650
570-0926 (7475) 1650
5
1650
570-0926 (7563)
4
1650
570-0928 (7570)
570-0928 (7474) 1650
570-0924 (7473) 1650
5 1650
570-0924 (7562)
570-0922 (7472) 1650
570-0922 (7471) 1650
5 1650
570-0922 (7561)
570-0921 (7495) 1650
570-0921 (7494) 1650
5
1650
570-0921 (7560)
570-0930 (7491) 1650
570-0930 (7490) 1650
5 1650
570-0930 (7559)
570-0920 (7470) 1650
570-0920 (7469) 1650
570-0919 (7489) 1650
570-0919 (7488) 1650
6
1650
550-0915 (7530)
550-0915 (7463) 1650
550-0915 (7462) 1650
550-0915 (7558) 1650
520-0905 (7457) 1650
520-0905 (7456) 1650
5 1650
520-0905 (7555)
520-0904 (7455) 1650
520-0904 (7454) 1650
5
1650
520-0904 (7554)
520-0903 (7453) 1500
520-0912 (7397) 1500
520-0912 (7395) 1500
520-0903 (7452) 1500
5
1500
520-0903 (7553)
520-0902 (7459) 1500
)
520-0902 (7458) 1500
5
1500
520-0902 (7552)
520-0901 (7451) 1500
520-0900 (7450) 1500
*Note: 1. 1.9MB - These models share L2 cache between 2 processors.
2. 36MB - These models share L3 cache between 2 processors.
3. CPU Range - Partial processor models, offering multiple price/performance points for the
entry market.
4. Capacity Backup model.
5. High Availability model.
6. Domino edition.
7. The MCU rating is a projected value.
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
L3 cache
L2 cache
CPU
2)
(
per CPU
(1)
Range
per CPU
1.9 MB 36 MB 8 - 16
1.9 MB 36 MB 8 - 16
1.9 MB 36 MB 13 - 16
1.9 MB 36 MB 13 - 16
1.9 MB 36 MB 13 - 16
1.9 MB 36 MB 2 - 16
1.9 MB 36 MB 9 - 12
1.9 MB 36 MB 9 - 12
1.9 MB 36 MB 9 - 12
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB 36 MB
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9 MB NA
1.9MB NA
1.9 MB NA
Appendix C CPW, CIW and MCU for System i Platform
Processor 5250 OLTP
CPW
24500-45500 12000-45500
24500-45500
36300-44700 12,000-44,700
36300-44700
36300-44700 12000-44,700
6350-44700 6,350-44,700
25500-33400 12,000-33,400
25500-33400
25500-33400
12000-44,700
5 - 8 15200-23500 12,000-23,500
5 - 8 15200-23500
5 - 8 15200-23500 12,000-23,500
2 - 4 6350-12000
2 - 4 6350-12000
2 - 4 6350-12000
1 - 2 3300-6000
1 - 2 3300-6000
1 - 2 3300-6000
2 - 4 6350-12000
2 - 4 6350-12000
1 - 2 3300-6000
1 - 2 3300-6000
2 - 4 6350-12000
1 - 4 3300-12000 3,300-12,000
1 - 4 3300-12000
1 - 4 3300-12000 3,300-12,000
2 6000
2 6000
2 6000 3,300-6,000
1 3300
1 3300
1 3300
1 2400
1 2400
1 2400
1 2400
1 2400
(3) 1000
1
(3)
1000
1
(3)
1000
1
(3)
1000
1
(3)
500
1
MCU
CPW
54000-104000
54000-104000
0
83600-102000
0 83600-102000
83600-102000
14100-102000
57300-77000
0 57300-77000
57300-77000
33600-52500
0 33600-52500
33600-52500
12000 14100-26600
14100-26600
0
12000 14100-26600
6000 7300-13300
0 7300-13300
6,000 7300-13300
Max 14100-26600
0 14100-26600
Max 7300-13300
0 7300-13300
0 14,100-26600
7300-26600
0 7300-26600
7300-26600
3,300-6000 13300
0 13300
13300
3,300 7300
0 7300
3,300 7300
2400 5500
60 5500
60 5500
0 5500
2400 5500
1000 2300
0 2300
1000 2300
60 2300
30 NA recommended
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