Model 810 And 825 Iseries For Domino (February 2003); V5R2 Additions; Base Models 8Xx Servers; Standard Models 8Xx Servers - IBM 170 Servers Manual

C.8.2 Model 810 and 825 iSeries for Domino (February 2003)
Table C.8.2.1. iSeries for Domino 8xx Servers
Chip Speed
Model
825-2473 (7416)
825-2473 (7416)
810-2469 (7428)
810-2467 (7410)
810-2466 (7407)
*Note: 1. 5250 OLTP CPW - With a rating of 0, adequate interactive processing is available for a
single 5250 job to perform system administration functions.
2. IBM does not intend to publish CIW ratings for iSeries after V5R2. It is recommended that
the eServer Workload Estimator be used for sizing guidance, available at:
http://www.ibm.com/eserver/iseries/support/estimator
na - indicates the rating is not available for the 4-way processor configuration
C.9 V5R2 Additions
In V5R2 the following new iSeries models were introduced:
890 Base and Standard models
840 Base models
830 Base and Standard models
Base models represent server systems with "0" interactive capability. Standard Models represent systems
that have interactive features available and also may have Capacity Upgrade on Demand Capability.
See Chapter 2, iSeries RISC Server Model Performance Behavior, for a description of the performance
highlights of the new Dedicated servers for Domino models.
C.9.1 Base Models 8xx Servers
Table C.9.1.1 Base Models 8xx Servers
Chip Speed
Model
890-0198 (none)
890-0197 (none)
840-0159 (none)
840-0158 (none)
830-0153 (none)
* 890 Models share L2 cache between 2 processors
C.9.2 Standard Models 8xx Servers
Standard models have an initial offering of processor and interactive capacity with featured upgrades for
activation of additional processors and increased interactive capacity. Processor features are offered
through Capacity Upgrade on Demand, described in C.10 V5R1 Additions.
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
©
Copyright IBM Corp. 2008
L2 cache CPU
MHz per CPU Range
1100 1.41 MB
1100 1.41 MB
4 MB
750
4 MB
750
2 MB
540
L2 cache
CPUs
MHz per CPU
1300 1.41 MB*
1300 1.41 MB*
600 16 MB
600 16 MB
540 4 MB
Appendix C CPW, CIW and MCU for System i Platform
5250 OLTP
Processor CPW
CPW*
6 6600
4 na
2 2700
1 1470
1 1020
Processor Interactive
CPW CPW
32 37400
24 29300
24 20200
12 12000
8 7350
Processor
CIW*
0 2890
0 na
0 950
0 530
0 380
Processor
CIW
0 16700 108900
0 12900
0 10950
0 5700
0 3220
MCU
17400
11600
7900
4200
3100
MCU
84100
77800
40500
20910
353