Jumper J1G2; Jumper J3E1; Jumper J3G1 - Intel IQ80219 Board Manual

Intel® IQ80219 General Purpose PCI Processor Evaluation Platform
Hardware Reference Section
3.10.9.19

Jumper J1G2

Table 76. Jumper J1G2: Descriptions
Jumper
J1G2
Table 77. Jumper J1G2: Settings and Operation Mode
J1G2
Pins 1,2
Pins 2,3
3.10.9.20

Jumper J3E1

Table 78. Jumper J3E1: Descriptions
Jumper
J3E1
Table 79. Jumper J3E1: Settings and Operation Mode
J3E1
Pins 1,2
Pins 2,3
3.10.9.21

Jumper J3G1

Initialization Device Select:
Used as a chip select during configuration read and write transactions on the secondary bus.
Applications that do not require access to the bridge configuration registers from the
secondary bus pull this pin low.
Table 80. Jumper J3G1: Descriptions
Jumper
J3G1
Table 81. Jumper J3G1: Settings and Operation Mode
J3G1
Pins 1,2
Pins 2,3
66
Association
Can isolated the PCI-X reset from getting to the
PPCI-X Reset
board.
P_RST (primary side reset) disconnected from reset circuitry.
P_RST (primary side reset) used to reset board.
Association
SPCI-X Clock Enables spread-spectrum on the SPCI-X clock.
Spread-spectrum enabled.
Spread-spectrum disabled.
Association
PCI-X Bridge S_IDSEL: Enables Bridge access from the SPCI-X side.
Uses S_IDSEL as chip select during configuration read and write transactions on the
secondary bus.
S_IDSEL is pulled down for application that do not require access to bridge configuration
registers from secondary bus.
Description
Operation Mode
Description
Operation Mode
Description
Operation Mode
Factory Default
2-3
Factory Default
2-3
Factory Default
2-3
Board Manual