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3.10.4
Jumper Summary
Table 31.
Jumper Summary
Jumper
J1G2
J3E1
J3G1
J9E1
J9F1
3.10.5
Connector Summary
Table 32.
Connector Summary
Connector
J1F1
J1G1
J7A1
J1C1
J2C1
J3C1
J2F1
J3F2
J3F1
J1A1
J1B1
J2H1
J6G1
J8H1
3.10.6
General Purpose Input/Output Header
The board has three programmable general-purpose I/O pins (GPIO 0-3 on the 80321). These pins are
connected to a 6-pin, 2.54 mm (0.100") header (connector J3F1).
Table 33.
GPIO Header (J3F1) Definition
Pin
1
2
3
Board Manual
Intel® IQ80219 General Purpose PCI Processor Evaluation Platform
Association
PPCI-X Reset
Can isolated the PCI-X reset from getting to the board.
SPCI-X Clock
Enables spread-spectrum on the SPCI-X clock.
PCI-X Bridge
Enables Bridge access from the SPCI-X side.
PCI-X Bridge
Enables Base Address Register (BAR).
Allows user to control initialization sequence on the
PCI-X Bridge
bridge.
RJ45 Network Connector for GbE NIC
RJ11 Serial Port Connector for UART
20-Pin JTAG Debug Connector
Logic analyzer Mictor Connector for SPCI-X Bus
Logic analyzer Mictor Connector for SPCI-X Bus
Logic analyzer Mictor Connector for SPCI-X Bus
Logic analyzer Mictor Connector for 80219 Peripheral Bus
Logic analyzer Mictor Connector for 80219 Peripheral Bus
General Purpose I/O (GPIO) Header – GPIO 0-2
Secondary PCI-X Expansion Slot
Secondary PCI-X Expansion Slot – Not Populated
Primary PCI/PCI-X Edge Connector
DDR DIMM Connector
Connector for Battery
Signal
Pin
GPIO0
4
GPIO1
5
GPIO2
6
Hardware Reference Section
Description
Description
Signal
GND
GND
GND
Factory Default
2-3
2-3
2-3
2-3
2-3
55
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