Counters - Measurement Computing LGR-5320 Series User Manual

LGR-5320 Series User's Guide

Counters

Parameter
Counter type
Number of channels
Inputs
Resolution (programmable)
Count Modes
Debounce times (programmable)
Timebase accuracy
Input voltage range
Input type
Input
characteristics
LGR-5325
only
Maximum input
voltage range
Input high voltage
Input low voltage
Receiver type
Configuration
LGR-5327/
5329 only
Common mode
input voltage range
Differential input
voltage range
Input sensitivity
Input hysteresis
Input impedance
Absolute
maximum input
voltage
Table 10. Counter specifications
Condition Specification
LGR-5325: Conventional

LGR-5327/5329: Conventional and Quadrature (x1, x2, x4)

4
LGR-5325: Counter, Up/Down, Gate
LGR-5327/5329: Phase A+/A–, Phase B+/B–, Index +/–
32-bit or 16-bit.
Up/down counting
Period/frequency counting
Modulo-N
Quadrature counting (LGR-5327/5329 only)
16 steps from 500 ns to 25 ms; positive or negative edge
sensitive; glitch detect mode or debounce mode
50 ppm
0 V to 5.5 V
TTL
49.9 KΩ pull-down resistor
–0.5 V to 7.0 V
2.0 V
0.8 V
Quad DIFF receiver
Each channel consists of Phase A input, Phase B input and Index
input, with each input switch selectable as SE or DIFF.
DIFF Phase A, Phase B and Index (+) inputs at user connector routed

to (+) inputs of the DIFF receiver.
Phase A, Phase B and Index (–) inputs at user connector routed

to (–) inputs of the DIFF receiver.
SE Phase A, Phase B and Index (+) inputs at user connector routed

to (+) inputs of DIFF receiver.
Phase A, Phase B and Index (–) inputs at user connector routed

to ground.
(–) inputs of DIFF receiver routed to +3 V reference.

±12 V max
±12 V max
±200 mV
50 mV typ
12 kΩ min
DIFF ±14 V max
34
Specifications