IBM EM78P809N Specification page 32

EM78P809N
8-Bit Microcontroller
Table 2. Mode Switching Control
Mode Switch
Normal
Sleep
Normal
Idle
Table 3. Operation Mode
Operation Mode
Signal
Clock
In NORMAL mode, the CPU core and on-chip peripherals operate in oscillator
frequency.
In IDLE mode, the CPU core halts, but the on-chip peripheral and oscillator circuit
remain active. IDLE mode is released to NORMAL mode by any interrupt source. If the
ENI instruction is set, an interrupt will be serviced first followed by executing the next
instruction which is after the IDLE mode is released and the interrupt service is finished.
If the ENI instruction is not set, the next instruction will be executed which is after the
IDLE mode start instruction. IDLE mode can also be released by setting the /RESET
pin to low and executing a reset operation.
In SLEEP mode, the internal oscillator is turned off and all system operation is halted.
SLEEP mode is released by /SLEEP pin (level sensitive or edge sensitive can be set by
System Control Register (SCR) bit 0 (REM)).
instruction will be executed which is after the SLEEP mode start instruction. SLEEP
mode can also be released by setting the /RESET pin to low and executing a reset
operation. In level sensitive mode, the /SLEEP pin must be confirmed in low level
before entering SLEEP mode. In edge sensitive mode, SLEEP mode is started even
when the /SLEEP pin is in high level.
Table 4. Wake-up Methods
Wake-up Signal
1. Individual interrupt source
in IMR1, IMR2
2. WDT interrupt request
3. /INT0
4. ENI instruction is not
executed
28 •
Sleep Set SIS = 1, execute SLEP instruction
Normal /SLEEP pin wake up
Idle Set SIS = 0, execute SLEP instruction
Normal Interrupt
Frequency
Reset
Turn on
Normal
Idle
Sleep Turn off
SLEEP Mode
R5 (SIS) = 1+SLEP
Instruction
No effect
Switch Method
CPU Code
Reset
Fosc
Halt
After a warm-up period, the next
IDLE Mode
R5 (SIS)= 0 + SLEP
Instruction
1. Wake-up
2. Jump to the next
(**) instruction or enter
IDLE mode
Product Specification (V1.0) 07.26.2005
(This specification is subject to change without further notice)
Note
On-chip
Peripherals
Reset
Fosc
Halt
NORMAL
Mode
R5 (SIS)=(*)
No effect
(**)