Cpu Operation Mode - IBM EM78P809N Specification

Bit 3 ( TBIE ) : Time base timer interrupt enable bit.
Bit 2 ( EXIE1 ) : External INT 1 Interrupt enable bit.
Bit 0 ( TCIE0 ) : TCC Interrupt enable bit.

4.4 CPU Operation Mode

Registers for CPU operation mode
R_BANK
BANK 0
* R_BANK: Register Bank (bits 7, 6 of R3), R/W: Read/Write
IDLE MODE
CPU : Halts
Fosc: Oscillates
Product Specification (V1.0) 07.26.2005
(This specification is subject to change without further notice)
TBIE = "0" : disable TBIF interrupt
TBIE = "1" : enable TBIF interrupt
EXIE1 = "0" : disable EXIF1 interrupt
EXIE1 = "1" : enable EXIF1 interrupt
TCIE0 = "0" : disable TCIF0 interrupt
TCIE0 = "1" : enable TCIF0 interrupt
Individual interrupt is enabled by setting its associated control bit in the IMR2
to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction.
IMR2 register is both readable and writable.
Address NAME
0X05
SCR
SIS=0 + SLEP
Interrupt
Fig 5. Operation Mode and Switching
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
0 PS2 PS1 PS0
-- R/W R/W R/W
Reset Occurs
SIS=1 + SLEP
NORMAL MODE
CPU : Operating
Fosc: Oscillates
/SLEEP Pin Input
EM78P809N
8-Bit Microcontroller
Bit 1 Bit 0
0 1
SIS REM
-- -- R/W R/W
SLEEP MODE
CPU : Halts
Fosc: Stops
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