Processor; L2 Cache; Main Memory - TMC TI7NBF User Manual

3.1 Processor

The TI7NBF motherboard is designed to take an Intel Celeron, Intel
Coppermine, or Cyrix III processors on the Socket 370 processor
connector.

3.2 L2 Cache

The L2 cache is integrated in the processor. The private L2 cache bus is
not connected to package pins; rather its signals are routed between the
two cavities using standard package techniques.

3.3 Main Memory

The TI7NBF motherboard supports three 168-pin DIMM (Dual In-line
Memory Module) sockets to form a memory configuration from 16MB to
384MB. DIMM modules can be 16MB, 32MB, 64MB and 128MB in
SDRAM DRAM. Examples on how to configure the memory are shown
in the table below.
NOTE: Use SDRAM modules with PC100 specification when running
100MHz CPU bus speed. With 66MHz CPU bus speed, SDRAM modules
with PC66 or PC100 specification can be used.
168-pin DIMM (3.3V) Unbuffer SDRAM
(DIMM1) (DIMM2) (DIMM3)
32MB -----
64MB -----
128MB -----
32MB 32MB
64MB 32MB
128MB 32MB
32MB 32MB
64MB 32MB
128MB 32MB
64MB 64MB
128MB 64MB
64MB 64MB
128MB 64MB
128MB 128MB
128MB 128MB
128MB 128MB
128MB 128MB
TI7NBF Socket 370 ATX Motherboard User's Manual
Chapter 3 Hardware Description
Total Memory
----- 32MB
----- 64MB
----- 128MB
----- 64MB
----- 96MB
----- 160MB
32MB 96MB
32MB 128MB
32MB 192MB
32MB 160MB
32MB 224MB
64MB 192MB
64MB 256MB
----- 320MB
32MB 288MB
64MB 320MB
128MB 384MB
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