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1.3.3 JTAG AC Timing Specifications
Table 8 provides the JTAG AC timing specifications.
Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C L = 50 pF, 0 ≤ T
Num
TCK frequency of operation
1
TCK cycle time
2
TCK clock pulse width measured at 1.4 V
3
TCK rise and fall times
4
TRST setup time to TCK rising edge
5
TRST assert time
6
Boundary-scan input data setup time
7
Boundary-scan input data hold time
8
TCK to output data valid
9
TCK to output high impedance
10
TMS, TDI data setup time
11
TMS, TDI data hold time
12
TCK to TDO data valid
13
TCK to TDO high impedance
Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Figure 5 provides the JTAG clock input timing diagram.
.
TCK
12
≤ 105 °C
J
Characteristic
3
3
VM = Midpoint Voltage (1.4 V)
Figure 5. Clock Input Timing Diagram
Preliminary—Subject to Change without Notice
Min
Max
0
16
62.5
—
25
—
0
3
13
—
40
—
6
—
27
—
4
25
3
24
0
—
25
—
4
24
3
15
1
2
VM
VM
603 Hardware Specifications, REV 2
Unit
Notes
MHz
ns
ns
ns
ns
1
ns
ns
2
ns
2
ns
3
ns
3
ns
ns
ns
ns
2
VM
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