Section 1.7, "System Design Information - IBM MPC603EC User Manual

1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603.
1.7.1 PLL Configuration
A 603 part number corresponds to a particular combination of internal (CPU core) and SYSCLK (external
bus) frequency ranges which the device has been tested to. The PLL is configured by the
PLL_CFG0–PLL_CFG3 pins. For a given SYSCLK (bus) frequency, the PLL configuration pins set the
internal CPU frequency of operation.
CPU/
PLL_CFG
SYSCLK
0–3
Ratio
00 00 1:1
0001 1:1
0010 1:1
0100 2:1
0101 2:1
1000 3:1
1001 3:1
1100 4:1
1101 4:1
0011
1111
Notes: 1. Some PLL configurations may select bus, CPU, or PLL frequencies which are not useful, not
supported, or not tested for by the 603. PLL frequencies (shown in parenthesis in Table 10) should
not fall below 133 MHz, and should not exceed 200 MHz.
2. In PLL bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is
disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use
only. Note that the AC timing specifications given in this document do not apply in PLL bypass
mode.
3. In clock-off mode, no clocking occurs inside the 603 regardless of the SYSCLK input.
4. PLL_CFG0–PLL_CFG1 signals select the CPU-to-bus ratio (1:1, 2:1, 3:1, 4:1),
PLL_CFG2–PLL_CFG3 signals select the CPU-to-PLL multiplier (x2, x4, x8).
603 Hardware Specifications, REV 2
Table 10. PLL Configuration
Bus, CPU, and PLL Frequencies
Bus Bus Bus
16.6 MHz 20 MHz 25 MHz
— —
— —
16.6 20
(133) (160) (200)
— —
33.3 40
(133) (160) (200)
— —
(150)
50 —
(200)
66.6 80 100
(133) (160) (200)
— —
Preliminary—Subject to Change without Notice
Bus Bus
33.3 MHz 40 MHz
— — —
— 33.3 40
(133) (160)
25 — —
— 66.6 80
(133) (160)
50 — —
75 100 —
(200)
— — —
— —
— — —
PLL bypass
Clock off
Bus Bus
50 MHz 66.6 MHz
— 66.6
(133)
50 —
(200)
— —
100 —
(200)
— —
— —
— —
— —
— —
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