Oki OKIPAGE 10ex Troubleshooting Manual page 8

3.2 CPU and Memory
(1) CPU (MHM2029-004K)
CPU core
CPU clock
Internal CPU CLK
(2) Program and Font ROMs
ROM capacity
ROM type
Access time
(3) Resident RAM
RAM capacity
RAM type
Access time
(4) Option Board
RAM capacity (chip)
RAM type (chip)
Access time (chip)
SIMM 1 socket
SIMM 2 socket
The block diagram of CPU and memory circuit is shown in Fig. 3-4.
The timing chart of CPU and memory ciucuit is shown in Fig. 3-5.
40990901TH Rev.1
RISC CPU (MIPS R3000 compatible)
7.067 MHz
28.268 MHz
6M bytes (24M bit mask ROM two pieces)
24M bits (1.5M x 16 bits)
100 ns
2M bytes (4-Mbit D-RAM four pieces)
4M bits (512k x 8 bits)
70 ns
1M byte
4M bits D-RAM two pieces
60 ns
2, 4, 8, 16 or 32M bytes, 72 pin DRAM SIMM, 60 to 100 ns
Flash SIMM (72 pin)
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Memory Expansion Board only
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