Dgps Receiver; Port Allocations - Icom FP-561 Service Manual

3-6 DGPS RECEIVER (RD-200)
3-6-1 ANTENNA CIRCUIT (ANT UNIT)
EP3 and EP4 consist of 2 series of antennas respectively
(total 4 series).
The received signal from the antenna (EP3) is tuned at C3,
and is amplified at the RF amplifier circuits (Q1, Q2, Q5, Q6).
On the other hand, the received signal from another antenna
(EP4) which falls at right angle with EP3, is tuned at C4. The
tuned signal is amplified at the RF amplifier circuits (Q3, Q4,
Q7, Q8).
The both amplified signals are piled up and are impedance-
matched to 50 at L1, and are then applied to the MAIN unit
via J1.
3-6-2 RF AMPLIFIER CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the ANT unit via J1 (pin 2) pass through the
low-pass filter (L2, L3, C3–C7) and high-pass filter (L4,
C8–C10). The filtered signals are amplified at the RF ampli-
fier (IC1) and are then enter another low-pass filter (L6, L7,
C15–C19) and notch filter (L24, L25, C111, C112) to sup-
press unwanted signals. The filtered signals are applied to
the mixer circuit.
3-6-3 MIXER CIRCUIT (MAIN UNIT)
The mixer circuit (IC2, L8, L9) is a double-balanced mixer
which converts the received signal to a fixed frequency of the
IF signal with an LO frequency.
The signals from the RF circuit are mixed with the LO signal
at the mixer circuit (IC2, L8, L9) to produce a 455 kHz IF sig-
nal.
3-6-4 IF CIRCUIT (MAIN UNIT)
By changing the LO frequency, only the desired frequency
will pass through the IF filter at the next stage of the mixer.
The IF signal from the mixer circuit is amplified at the IF
amplifier (Q1) and is applied to a ceramic filter (FI1) to sup-
press out-of-band signals. The filtered signal is applied to the
FM IF IC circuit (IC3).
3-6-5 DEMODULATOR CIRCUIT (MAIN UNIT)
The FM IF IC (IC3) contains the limiter amplifier, detector cir-
cuits, etc.
The IF signal from the IF filter is applied to the limitter ampli-
fier section of IC3 (pin 5). The amplified signal is mixed with
a 456.2 kHz signal from CPU IC (IC12) to produce a 1.2 kHz
detector signal for demodulation the IF signal into AF signals.
AF signal from FM IF IC (IC3, pin 9) passes through the low-
pass filter (IC4a, IC4b). The filtered signal is amplified at the
AF amplifier (Q4) and is applied to the CPU (IC12).
3-6-6 REFERENCE OSCILLATOR CIRCUIT
(MAIN UNIT)
The reference oscillator circuit generates the reference fre-
quency, and the signals are applied to the DDS IC and CPU.
The generated reference signal from the reference oscillator
(X1: 14.5984 MHz) is amplified and divided at the buffer
amplifier (IC7). The divided signal (7.2992 MHz) is applied to
the DDS IC (IC6) and CPU (IC12) via the amplifiers IC5, IC10
respectively.
3-6-7 LO CIRCUIT (MAIN UNIT)
The LO circuit generates the LO frequency, and the signals
are applied to the mixer circuit.
The generated LO signal is output from IC6 and passed
through the D/A converter (R26–R45), low-pass filter (L15,
L16, C55–C59) and high-pass filter (L17, C60–C62). The fil-
tered signal is amplified at the buffer amplifier (Q2) and then
is passed through the low-pass filter (L18, L19, C65–C69).
The filtered signal is applied to the mixer circuit.

3-7 PORT ALLOCATIONS

3-7-1 FP-561
• SUB CPU (LOGIC UNIT; IC22)
Pin Port
number name
Outputs Tx (50 kHz/200 kHz) pulse sig-
1 TXSIG
nals to IC1 (pins 1, 3).
Outputs control signal for LCD back-
3 INV
light.
Outputs control signal for the LCD con-
4 CONT
trast
A/D input port for the received signal
7 RSSI
strength indicator voltage.
Input port for serial signal from the
16 GPSI GPS unit via the buffer amplifier (IC23,
pin 12).
Outputs serial signal to the buffer
17 GPSO
amplifier (IC23, pin 3) for the GPS unit.
Input port for serial signal from the
18 NMEAI
NMEA/DGPS units via the analog
switch (IC41, pin 14).
Outputs serial signal to the analog
20 NMO switch
NMEA/DGPS units.
Ship speed input port from the photo
72 SPD
coupler (IC7, pin 7) on the MAIN unit.
Outputs beep audio to the buzzer cir-
74 BEEP
cuit (Q4, SP1) on the SW unit.
Outputs receive frequency switching
77 LOC
signal for the analog switch (IC16).
Outputs trasmit triger signal for the dri-
80 TXTRG
ver circuit (IC2, pins 2, 6) on the MAIN
unit.
3 - 4
Description
(IC41, pin 2) for the