MSI MS-9297 User Manual page 28

1u rackmount server
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System Assembly
System Assembly
1 DIMM
2 DIMMs
3 DIMMs
4 DIMMs
5 DIMMs
6 DIMMs
7 DIMMs
8 DIMMs
9 DIMMs
10 DIMMs
11 DIMMs
12 DIMMs
2-10
Memory Population Rules
CPU1_DIMM1 (Channel A0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) +
CPU1_DIMM3 (Channel C0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) +
CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) +
CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0) +
CPU1_DIMM6 (Channel C1)
CPU1_DIMM1 (Channel A0) + CPU2_DIMM1 (Channel A0) +
CPU1_DIMM4 (Channel A1) + CPU2_DIMM4 (Channel A1) +
CPU1_DIMM2 (Channel B0) + CPU2_DIMM2 (Channel B0) +
CPU1_DIMM5 (Channel B1) + CPU2_DIMM5 (Channel B1) +
CPU1_DIMM3 (Channel C0) + CPU2_DIMM3 (Channel C0) +
CPU1_DIMM6 (Channel C1) + CPU2_DIMM6 (Channel C1)

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