Fujitsu EVB JADE-­D Manual page 14

Prepared
Manfred Ortmann
Approved
Pin
71
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75
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84
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102
103
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105
Document Number
Checked Date
2009­10­05
Signal
APIXGND Ground for APIX signals
SPI_SS0 SPI0 Master Slave Select
VIN0_7 Video Capture Data Input 0 bit 7
SPI_SCK0 SPI0 Master serial clock
VIN0_4 Video Capture Data Input 0 bit 4
TSG_R_4 TCON Timing Signal
VIN0_3 Video Capture Data Input 0 bit 3
TSG_R_5 TCON Timing Signal
VIN0_5 Video Capture Data Input 0 bit 5
TSG_R_6 TCON Timing Signal
VIN0_6 Video Capture Data Input 0 bit 6
DCLKP RSDS Clock Output CLKp, in TTL Mode
VIN0_1 Video Capture Data Input 0 bit 1
DCLKN RSDS Clock Output CLKn, in TTL Mode
VIN0_2 Video Capture Data Input 0 bit 2
DE0 TCON Bypass: DE/CSYNC of DISPL0, TCON:TSG_2
VIN0_8 Video Capture 0 Clock
HSYNC0 Video Capture 0 Horizontal Syncronisation
VIN0_0 Video Capture Data Input 0 bit 0
GVO0 Video output interface 0 graphics / video switch
TSG_R_7 TCON Timing Signal
VSYNC0 TCON Bypass: Video output interface 0 vertical sync
output vertical sync input in external sync mode
ATST_R APIX analog Test Clock
DOUTB1_R_5 Digital RGB output1 with serial resistor
PWMO2 PWM Output
DOUTB1_R_2 Digital RGB output1 with serial resistor
DOUTB1_R_3 Digital RGB output1 with serial resistor
DOUTG1_R_3 Digital RGB output1 with serial resistor
DOUTB1_R_4 Digital RGB output1 with serial resistor
DOUTB1_R_6 Digital RGB output1 with serial resistor
DOUTB1_R_7 Digital RGB output1 with serial resistor
DOUTG1_R_7 Digital RGB output1 with serial resistor
DOUTG1_R_2 Digital RGB output1 with serial resistor
DOUTG1_R_4 Digital RGB output1 with serial resistor
DOUTG1_R_5 Digital RGB output1 with serial resistor
Preliminary
Revision Storage
PA 4.2 Mycable01
Function
14(45)