5.
WD Circuit
Cl5
.-
RlO
R12
1
IC4
@-+
C6
R5
Id
IC6
@
--&"
D18
i
I__
07
L-__
;
Q8
J
Cl7
IC
(R eset state = 2 to 3 sec. Q
)
l
When
the WD
circuit
detects
abnormal
condition
on data communication
between
TEL
and Link switch
address output,
the WD
circuit
executes
system
reset with
sending out @
status on ICI-FIST
(pin No.26)
-
and IC4 to 6-RST
l
WD
circuit
is monitor
the status of data communication
Inh signal of IC4 and address output
of IC6 all
times,
in case of either
signals are stop, and the circuit
executes
system reset with
a following
operation
sequence:
ICI9
(pin No. 12or
13) is@+
ICI9
(pin No. 11) is@
-+ ICI9
(pin No. 10) is@
+ Qi'
[OFF1 -08
[ONI
-+
ICI9
(pin No, 4) is @
+ ICI9
(pin No. 3) is 0
+ ICI
(pin No. 26) is RST.
-6-