HP Integrity Superdome Servers 16- processor Systems Overview page 50

QuickSpecs
Configuration
Category Category Rule Index Rule Index
Category Category Rule Index Rule Index
General General General General
Processor Processor Processor Processor
Memory Memory Memory Memory
I/O I/O I/O I/O
Performance Performance Performance Performance
Rule Description Rule Description
Rule Description Rule Description
1 Every Superdome complex requires connectivity to a Support Management Station (SMS). The
PC-based SMS also serves as the system console.
2 Every cell in a Superdome complex must be assigned to a valid physical location.
3 All processors in a cell are the same type, same Front Side Bus (FSB) frequency, and same core
frequency.
4 Configurations with 8, 16 and 32 DIMM slots are recommended (i.e. are fully qualified and
offer the best bandwidth performance.)
5 Configurations with 4 and 24 DIMM slots are supported (i.e. are fully qualified, but don't
necessarily offer the best bandwidth performance).
6 DIMMs can be deallocated in 2 DIMM increments (to support HA).
7 Mixed DIMM sizes within a cell board are supported, but only in separate Mbat interleaving
groups.
8 System orders from the factory provide mixed DIMM sizes in recommended configurations only.
9 For system orders from the factory, the same memory configuration must be used for all cells
within a partition.
10 DIMMs in the same rank must have SDRAMs with the same number of banks and row and
column bits.
11 Size of memory within an interleave group must be power of 2.
12 DIMMs within the same interleave group must be same size and have same number of banks,
row bits, and column bits.
13 There are currently no restrictions on mixing DIMMs (of the same type) with different vendor
SDRAMs.
14 One cell in every partition must be connected to an I/O chassis that contains a Core I/O card,
a card connected to boot media, a card connected to removable media, and a network card
with a connected network.
15 A partition cannot have more I/O chassis than it has active cells.
16 Removable media device controller should be in slot 8 of the I/O chassis.
17 Core I/O card must be in slot 0 of the I/O chassis.(sx2000 systems do not have a core I/O)
18 Boot device controller should be in slot 1 of the I/O chassis
19 PCI-X high bandwidth I/O cards should be in the high bandwidth slots in the I/O chassis
20 Every I/O card in an I/O chassis must be assigned to a valid physical location.
21 Every I/O chassis in a Superdome complex must be assigned to a valid physical location
22 The amount of memory on a cell should be evenly divisible by 4 GB if using 512-MB DIMMs or
8 GB if using 1-GB DIMMs, i.e. 8, 16 or 32 DIMMs. The cell has four memory subsystems and
each subsystem should have an echelon (2 DIMMs) populated. The loading order of the
DIMMs alternates among the four subsystems. This rule provides maximum memory bandwidth
on the cell, by equally populating all four memory subsystems.
23 All cells in a partition should have the same number of processors.
24 The number of active processors per cell should be balanced across the partition, however
minor differences are OK. (Example: 4 active processors on one cell and three active
processors on the second cell)
25 If memory is going to be configured as fully interleaved, all cells in a partition should have the
same amount of memory (symmetric memory loading). Asymmetrically distributed memory
affects the interleaving of cache lines across the cells. Asymmetrically distributed memory can
create memory regions that are non optimally interleaved. Applications whose memory pages
land in memory interleaved across just one cell can see up to 16 times less bandwidth than
ones whose pages are interleaved across all cells.
DA - 11717 Worldwide — Version 35 — December 6, 2006
HP Integrity Superdome Servers 16- processor, 32- HP Integrity Superdome Servers 16- processor, 32- HP Integrity Superdome Servers 16- processor, 32- HP Integrity Superdome Servers 16- processor, 32-
processor, and 64- processor Systems processor, and 64- processor Systems processor, and 64- processor Systems processor, and 64- processor Systems
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