HP 9000 rp7440 Quickspecs page 7

QuickSpecs
Configuration
Performance Tuning Performance Tuning Performance Tuning Performance Tuning
Guidelines Guidelines Guidelines Guidelines
Memory Latencies Memory Latencies Memory Latencies Memory Latencies
Number of Processors Per Partition
4 processor (single cell)
8 processor (two cell)
I/O Architecture I/O Architecture I/O Architecture I/O Architecture
For best performance, a cell should be configured with a multiple of eight DIMMs or four pairs
(although the server will execute properly with an odd number of pairs). It takes eight DIMMs to
populate both memory buses. Populating only one of the two memory buses on a cell board will
deliver only half the peak memory bandwidth.
Load memory equally across the available cell boards.
There are two types of memory latencies within the HP 9000 rp7440 Server:
1. Memory latency within within within within the cell refers to the case where an application either runs on a partition
that consists of a single cell or uses cell local memory.
2.
Memory latency between between between cells refers to the case where the partition consists of two cells and cell between
interleaved memory is used. In this case 50% of the addresses are to memory on the same cell as
the requesting processor, and the other 50% of the addresses are to memory of the other cell.
The HP 9000 rp7440 Server average memory latency depends on the number of CPUs in the partition.
Assuming that memory accesses are equally distributed across all cell boards and memory controllers
within the partition, the average idle memory latency (load to use) is as show below:
Components within the I/O subsystem are the I/O controllers, internal peripheral bay, and multifunction
Core I/O. The figure below shows the basic block diagram of the I/O subsystem. The HP 9000 rp7440
Server I/O architecture utilizes industry standard PCI X buses in a unique design for maximum
performance, scalability and reliability.
The HP 9000 rp7440 Server contains two master I/O controller chips located on the PCI X backplane.
Each I/O controller contains 16 high performance, 12 bit wide links; these links connect to 18 slave I/O
controller chips supporting the PCI card slots and core I/O. In the HP 9000 rp7440 Server, two links,
one from each master controller, are routed through the system backplane and are dedicated to core
I/O. The remaining 30 links are divided among the sixteen (133 MHz; 64 bit and 266 MHz; 64 bit) PCI
X card slots, with each slot on a PCI bus by itself. This one card per bus architecture leads to greater I/O
performance, better error containment, and higher availability.
Each controller chip is also directly linked to a host cell board. This means that both cell boards must be
purchased in order to access all 15 available I/O card slots. (With only one cell board, access to seven
slots is enabled.)
The HP 9000 rp7440 Server can be purchased with either one or two core I/O board sets. Each Core
I/O product contains two boards, a MP/SCSI and a LAN/SCSI card. The core I/O boards provide
console, Ultra320 SCSI, Gigabit LAN, and management processor functionality. If you opt for the
second core I/O board set, it can be used to enable dual hard partitioning (nPars) in the HP 9000
rp7440 Server and to provide access to a second set of disk drives. Two cell boards and access to all
I/O slots are available to the server with one core I/O board set.
The LAN/SCSI card provided with each Core I/O product occupies one of the sixteen PCI slots. Since
there must always be at least one Core I/O board set, the HP 9000 rp7440 Server has fifteen available
PCI X slots for expansion cards. If the second Core I/O product (board set) is purchased, there are
fourteen remaining slots available for cards.
DA - 12696 North America — Version 4 — March 3, 2008
Average Memory Latency Average Memory Latency Average Memory Latency Average Memory Latency
~185 ns
~249 ns
HP 9000 rp7440 Server HP 9000 rp7440 Server HP 9000 rp7440 Server HP 9000 rp7440 Server
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